210 lines
11 KiB
Markdown
210 lines
11 KiB
Markdown
# CM5 Carrier — Authoritative Pin Map (CM5 ↔ Carrier Nets)
|
||
|
||
**Source of truth:** `refs/CM5IO.kicad_sym`, symbol `ComputeModule5-CM5` (official Raspberry Pi CM5 IO Board rev 2 KiCad files). All 200 connector pins parsed directly from the symbol — these are the real pin numbers a layout engineer maps to.
|
||
|
||
**Connector model:** the CM5 mates via two 100-pin Hirose DF40 connectors. In the symbol, pins **1–100** are one connector strip and **101–200** the other. KiCad resolves the physical split from the footprint; the pin *numbers* below are what the netlist uses.
|
||
|
||
Companion to `CM5_Carrier_Design.md` and `CM5_Carrier_Pinout_BOM.md`. **This file supersedes** the "by datasheet net name" placeholders in those docs.
|
||
|
||
---
|
||
|
||
## 0. Corrections found during pin verification (read first)
|
||
|
||
Mapping the real symbol exposed three errors in the earlier `CM5_Carrier_Pinout_BOM.md`:
|
||
|
||
| # | Prior doc said | Reality (from symbol) | Impact |
|
||
|---|----------------|------------------------|--------|
|
||
| **C1** | CM5 SYNC is **1.8 V**, needs a 3V3→1V8 level translator (SN74LVC1T45) on the PPS path | Pin 18 is **`Ethernet_SYNC_OUT(3.3v)`** — 3.3 V signalling | **Delete the level translator (U_LVLSHIFT).** 3.3 V GPS PPS → Schmitt → drives pin 18 directly. Removes a part and a gotcha. |
|
||
| **C2** | Debug UART uses "dedicated debug pins on the DF40"; NMEA GPS can take GPIO14/15 (UART0) | **No dedicated debug-UART pins exist.** The only console UART is GPIO14/15 (UART0). Reference board has no debug-UART connector. | **Conflict.** Keep debug console on GPIO14/15; **move NMEA GPS to UART2 (GPIO4/5).** |
|
||
| **C3** | Fan is "optional, keep from ref" with no pin assignment | Dedicated **`FAN_PWM` (pin 19)** + **`FAN_TACHO` (pin 16)** exist | Fan header wires to pins 19/16, not GPIO. |
|
||
|
||
Also confirmed useful: CM5 **sources** `+3.3V` (pins 84/86) and `+1.8V` (88/90); there's a dedicated `VBAT` (76) for RTC backup, and `GPIO_VREF` (78) **must be driven** to set the GPIO bank level.
|
||
|
||
---
|
||
|
||
## 1. Power & control pins
|
||
|
||
| CM5 pin(s) | Net | Direction | Carrier connection |
|
||
|-----------|-----|-----------|--------------------|
|
||
| 77, 79, 81, 83, 85, 87 | `+5v_(Input)` | **in** to CM5 | **+5V** from `U_BUCK5` (main module supply). Decouple per datasheet; all 6 pins tied. |
|
||
| 84, 86 | `+3.3v_(Output)` | out of CM5 | CM5-sourced 3.3 V (limited current). Usable for `GPIO_VREF`, light pull-ups. **Do not** power the AW7915 from this. |
|
||
| 88, 90 | `+1.8v_(Output)` | out of CM5 | CM5-sourced 1.8 V. Spare; route to a test point. |
|
||
| 78 | `GPIO_VREF(1.8v/3.3v_Input)` | **in** to CM5 | **Tie to 3.3 V** (from CM5 `+3.3v` out or `+3V3_AUX`) to set the 40-pin bank to 3.3 V logic. |
|
||
| 76 | `VBAT` | **in** to CM5 | RTC backup: CR2032 (BT1) via ORing/diode. |
|
||
| 99 | `PMIC_ENABLE` | in | → J2 pin 12. Power enable/disable. |
|
||
| 92 | `PWR_BUT` | in | → J2 pin 13 wake/shutdown push-button. |
|
||
| 93 | `nRPIBOOT` | in | → J2 pin 1 jumper **and** boot-select for USB-C rpiboot. |
|
||
| 20 | `EEPROM_nWP` | in | → J2 pin 3 EEPROM write-protect jumper. |
|
||
| 95 | `LED_nPWR` | out | Power LED (sink). |
|
||
| 21 | `LED_nACT` | out | Activity LED (sink). |
|
||
| 111 | `VBUS_EN` | out | USB host VBUS enable → gates USB-A VBUS load switch. |
|
||
| 94 / 96 | `CC1` / `CC2` | — | Module USB-C CC lines. **See §6 note** — our USB-C is data/rpiboot only; verify against reference wiring. |
|
||
| 1,2,7,8,13,14,22,23,32,33,42,43,52,53,59,60,65,66,71,74,98,107,108,113,114,119,120,125,126,131,132,137,138,144,150,155,156,161,162,167,168,173,174,179,180,185,186,191,192,197,198 | `GND` (51 pins) | — | Stitch to ground plane. |
|
||
|
||
---
|
||
|
||
## 2. Ethernet (CM5 on-module BCM54210PE → magjack)
|
||
|
||
No external PHY. 1:1 magjack + ESD. 100 Ω diff pairs.
|
||
|
||
| CM5 pin | Net | Magjack |
|
||
|---------|-----|---------|
|
||
| 12 / 10 | `Ethernet_Pair0_P` / `_N` | MDI0 ± |
|
||
| 4 / 6 | `Ethernet_Pair1_P` / `_N` | MDI1 ± |
|
||
| 11 / 9 | `Ethernet_Pair2_P` / `_N` | MDI2 ± |
|
||
| 3 / 5 | `Ethernet_Pair3_P` / `_N` | MDI3 ± |
|
||
| 17 | `Ethernet_nLED2(3.3v)` | Link/activity LED |
|
||
| 15 | `Ethernet_nLED3(3.3v)` | Speed LED |
|
||
| **18** | **`Ethernet_SYNC_OUT(3.3v)`** | **IEEE 1588 timing — 3.3 V, bidirectional → PPS block (see §5)** |
|
||
|
||
Magjack PoE center-tap pins: **NC** (no PoE). Bob-Smith termination + ESD array on cable side.
|
||
|
||
---
|
||
|
||
## 3. PCIe ×1 Gen2 → M.2 E-key (Wi-Fi, AW7915)
|
||
|
||
| CM5 pin | Net | E-key |
|
||
|---------|-----|-------|
|
||
| 110 / 112 | `PCIe_CLK_P` / `_N` | REFCLK ± (100 MHz) |
|
||
| 116 / 118 | `PCIe_RX_P` / `_N` | card→host (PER ±). **AC-couple caps on carrier.** |
|
||
| 122 / 124 | `PCIe_TX_P` / `_N` | host→card (PET ±). AC-coupled on CM5 side. |
|
||
| 109 | `PCIe_nRST` | PERST# |
|
||
| 102 | `PCIe_nCLKREQ` | CLKREQ# |
|
||
| 104 | `PCIE_nWAKE` | PEWAKE# (optional; pull-up) |
|
||
| 106 | `PCIE_PWR_EN` | gate for E-key 3.3 V enable (optional) |
|
||
|
||
E-key 3.3 V (W_DISABLE rail / VCC) ← **`+3V3_RF`** (dedicated 15→3.3 V 4 A buck). E-key USB pins **NC** (Wi-Fi only, no BT). PCIe pairs ~85 Ω diff; length-match; REFCLK matched pair.
|
||
|
||
---
|
||
|
||
## 4. USB
|
||
|
||
| CM5 pins | Net | Goes to |
|
||
|----------|-----|---------|
|
||
| 130/128, 142/140, 134/136 | `USB3-0-RX_P/N`, `USB3-0-TX_P/N`, `USB3-0-D_P/N` | **USB-A #1** (SS RX/TX pairs + USB2 D±) |
|
||
| 159/157, 171/169, 163/165 | `USB3-1-RX_P/N`, `USB3-1-TX_P/N`, `USB3-1-D_P/N` | **USB-A #2** |
|
||
| 105 / 103 | `USB2_P` / `USB2_N` | **USB-C** (rpiboot/programming) |
|
||
| 101 | `USB_OTG_ID` | USB-C OTG ID (or NC/strap for device mode) |
|
||
|
||
USB-A VBUS via current-limit load switch gated by `VBUS_EN` (pin 111). ESD (USBLC6-class) on each external port. SS pairs ~90 Ω diff.
|
||
|
||
---
|
||
|
||
## 5. PPS / timing distribution (corrected — no level shifter)
|
||
|
||
Board is a **PPS sink**; GPS is the only source. **SYNC is 3.3 V** (pin 18) so the path is all-3.3 V:
|
||
|
||
```
|
||
J_GPS.PPS (3V3) ─► [TVS] ─► [Schmitt LVC1G17, 3V3] ─► PPS_CLEAN(3V3) ─┬─► [Rs] ─► CM5 pin 18 (Ethernet_SYNC_OUT, cfg as input)
|
||
├─► J_PPS1 (UWB tap)
|
||
└─► J_PPS2 (scope/spare tap)
|
||
```
|
||
|
||
- **No 3V3→1V8 translator** (correction C1). Delete `U_LVLSHIFT` / SN74LVC1T45 from the BOM.
|
||
- Add a small **series resistor `Rs`** (e.g. 33–100 Ω) between the Schmitt output and pin 18: pin 18 is bidirectional, so Rs prevents a driver fight if firmware ever configures it as output. Board config is always input.
|
||
- Schmitt + TVS still wanted: square the off-board GPS edge, protect the pin.
|
||
|
||
| Net | From | To | Level |
|
||
|-----|------|----|-------|
|
||
| `GPS_PPS_RAW` | J_GPS.1 | TVS → Schmitt in | 3.3 V |
|
||
| `PPS_CLEAN` | Schmitt out | fan-out ×3 | 3.3 V |
|
||
| `PPS_SYNC` | via Rs | CM5 pin 18 | 3.3 V |
|
||
| `NMEA_TX` | CM5 GPIO4 (UART2 TX) | J_GPS.RX | 3.3 V |
|
||
| `NMEA_RX` | CM5 GPIO5 (UART2 RX) | J_GPS.TX | 3.3 V |
|
||
|
||
---
|
||
|
||
## 6. UART assignments (corrected — C2)
|
||
|
||
There is **one console UART** on GPIO14/15 and no dedicated debug pins. So:
|
||
|
||
| Function | CM5 UART | GPIO (BCM) | CM5 pins | 40-pin header | Connector |
|
||
|----------|----------|-----------|----------|---------------|-----------|
|
||
| **Debug console** | UART0 | GPIO14 (TXD0) / GPIO15 (RXD0) | 55 / 51 | pins 8 / 10 | J_UART (3-pin tap) |
|
||
| **NMEA GPS** | UART2 | GPIO4 / GPIO5 | 54 / 34 | pins 7 / 29 | J_GPS (via dtoverlay `uart2`) |
|
||
|
||
NMEA on UART2 keeps the console free. GPIO4/5 still appear on the 40-pin (shared net) — document that pins 7/29 are committed to GPS when fitted. PPS edge does **not** use a UART — it's the dedicated SYNC pin 18.
|
||
|
||
> USB-C CC note: the module exposes `CC1`/`CC2` (pins 94/96). Our USB-C is data-only for rpiboot; put 5.1 kΩ pulldowns at the USB-C connector for UFP/sink detection. Before finalizing, check how `refs/CM5IO.kicad_sch` ties module CC1/CC2 (the reference uses USB-C as a power path; we don't) — likely leave module CC pins per reference or NC.
|
||
|
||
---
|
||
|
||
## 7. 40-pin GPIO header — CM5 pin behind each BCM GPIO
|
||
|
||
The 40-pin positions are standard (see `CM5_Carrier_Pinout_BOM.md` §2). This table gives the **CM5 connector pin** behind each GPIO so the layout can route header→module directly.
|
||
|
||
| BCM | CM5 pin | 40-pin pos | Alt / use here |
|
||
|-----|---------|-----------|----------------|
|
||
| GPIO2 | 58 | 3 | I2C1 SDA |
|
||
| GPIO3 | 56 | 5 | I2C1 SCL |
|
||
| GPIO4 | 54 | 7 | **UART2 TX → NMEA** |
|
||
| GPIO5 | 34 | 29 | **UART2 RX → NMEA** |
|
||
| GPIO6 | 30 | 31 | |
|
||
| GPIO7 | 37 | 26 | SPI0 CE1 |
|
||
| GPIO8 | 39 | 24 | SPI0 CE0 |
|
||
| GPIO9 | 40 | 21 | SPI0 MISO |
|
||
| GPIO10 | 44 | 19 | SPI0 MOSI |
|
||
| GPIO11 | 38 | 23 | SPI0 SCLK |
|
||
| GPIO12 | 31 | 32 | PWM0 |
|
||
| GPIO13 | 28 | 33 | PWM1 |
|
||
| GPIO14 | 55 | 8 | **UART0 TXD → debug** |
|
||
| GPIO15 | 51 | 10 | **UART0 RXD → debug** |
|
||
| GPIO16 | 29 | 36 | |
|
||
| GPIO17 | 50 | 11 | |
|
||
| GPIO18 | 49 | 12 | PCM_CLK |
|
||
| GPIO19 | 26 | 35 | PCM_FS |
|
||
| GPIO20 | 27 | 38 | PCM_DIN |
|
||
| GPIO21 | 25 | 40 | PCM_DOUT |
|
||
| GPIO22 | 46 | 15 | |
|
||
| GPIO23 | 47 | 16 | |
|
||
| GPIO24 | 45 | 18 | |
|
||
| GPIO25 | 41 | 22 | |
|
||
| GPIO26 | 24 | 37 | |
|
||
| GPIO27 | 48 | 13 | |
|
||
| ID_SD (GPIO0) | 36 | 27 | HAT EEPROM I2C0 SDA |
|
||
| ID_SC (GPIO1) | 35 | 28 | HAT EEPROM I2C0 SCL |
|
||
|
||
Other I²C: `SCL0`/`SDA0` (pins 80/82) = I2C0 (camera/HAT-ID domain); `CAM_GPIO0`/`1` (97/100) — route to test points or leave NC (no camera).
|
||
|
||
---
|
||
|
||
## 8. Fan, radio-disable, RTC
|
||
|
||
| CM5 pin | Net | Use |
|
||
|---------|-----|-----|
|
||
| 19 | `FAN_PWM` | → J_FAN PWM (dedicated, not GPIO) |
|
||
| 16 | `FAN_TACHO` | → J_FAN tach |
|
||
| 89 | `WiFi_nDisable` | If a **wireless** CM5 is fitted, tie low to disable onboard radio (E-key is our Wi-Fi). With non-wireless CM5: NC. Mirrors ref J3. |
|
||
| 91 | `BT_nDisable` | As above for BT. |
|
||
| 76 | `VBAT` | CR2032 (BT1) → CM5 on-module RTC backup |
|
||
|
||
CM5 has an **on-module RTC** — the carrier only supplies the backup cell on `VBAT`. No external I²C RTC needed (drop the optional PCF85063A mention).
|
||
|
||
---
|
||
|
||
## 9. Explicitly unused / NC pin groups
|
||
|
||
Deleted features — leave these CM5 pins **No-Connect**:
|
||
|
||
| Group | CM5 pins | Why NC |
|
||
|-------|----------|--------|
|
||
| HDMI0/HDMI1 | 143,145,146,147,148,149,151,152,153,154,158,160,164,166,170,172,176,178,182,184,188,190,199,200 | No display out |
|
||
| MIPI0 (DSI/CSI) | 115,117,121,123,127,129,133,135,139,141 | No display/camera |
|
||
| MIPI1 (DSI/CSI) | 175,177,181,183,187,189,193,194,195,196 | No display/camera |
|
||
| microSD | 57,61,62,63,64,67,68,69,70,72 (SD_*) + 73 (`SD_VDD_Override`), 75 (`SD_PWR_ON`) | eMMC module; no SD card |
|
||
|
||
> If a **camera** is ever wanted, MIPI0 (pins 115–141) is the block to revive — flagged in design doc as the only realistic add-back.
|
||
|
||
---
|
||
|
||
## 10. What changed in the companion docs
|
||
|
||
Apply these so all three files agree (done in markdown; the **`.xlsx` BOM still lists `U_LVLSHIFT` and should drop it**):
|
||
|
||
- `CM5_Carrier_Pinout_BOM.md` §3, §6, §12: SYNC is 3.3 V; remove level-shifter; PPS drives pin 18 via series R.
|
||
- NMEA moved to UART2 (GPIO4/5); debug stays UART0 (GPIO14/15).
|
||
- Add FAN_PWM/TACHO (pins 19/16) to the fan header net.
|
||
- BOM: **delete line 15 (U_LVLSHIFT, SN74LVC1T45)**; add one 0402 series R on PPS→SYNC.
|
||
</content>
|
||
</invoke>
|