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# CM5 Carrier Board — Design Document
**Purpose:** Lean, deployable PTP/instrumentation compute node built on the Raspberry Pi Compute Module 5. Wired gigabit, on-board Wi-Fi via M.2 E-key, 15 V supply input, and the timing/boot/power signals of the official CM5IO J2 header broken out.
**Status:** Spec frozen (rev A scope). Ready for schematic capture.
**Target applications driving the design:** (1) external GPS-PPS disciplining an on-board PTP grandmaster; (2) UWB (Arduino prototype) wireless time-sync R&D referenced against GPS truth; (3) MT7915-based transparent Wi-Fi bridge. All three lean on a clean, distributable PPS timing path — hardened in this rev.
**Named Wi-Fi target:** AsiaRF **AW7915** (MediaTek MT7915, mt76 driver) — chosen for mac80211 AP / 4-address(WDS) support needed by the transparent bridge. Being proven out on the bench separately.
---
## 1. Design intent
A purpose-built carrier that strips the official CM5IO down to essentials and re-targets it for a powered-by-15V, time-synchronized node:
- **Keep:** the CM5's own gigabit PHY, one PCIe lane (→ Wi-Fi), USB, GPIO, RTC, timing.
- **Drop:** HDMI/MIPI display, on-board NVMe (M-key), microSD, PoE.
- **Add:** 15 V → 5 V front-end with reverse protection; M.2 E-key for a Wi-Fi card; both spare USB exposed as sockets.
The CM5 module carries its own Gigabit Ethernet PHY (Broadcom BCM54210PE) and the wireless radio option, so no external PHY is needed and the single PCIe Gen2 ×1 lane is free for the E-key Wi-Fi card.
---
## 2. Feature list (frozen)
| # | Feature | Implementation |
|---|---------|----------------|
| 1 | 15 VDC input | Jack or 2-pin → ideal-diode reverse-polarity FET + TVS → 15→5 V synchronous buck, 5 A |
| 2 | Gigabit Ethernet | CM5 on-module BCM54210PE → 1:1 RJ45 magjack + ESD. No external PHY. |
| 3 | M.2 E-key (Wi-Fi only) | PCIe ×1 Gen2 + CLKREQ/PERST/RF_KILL + 3.3 V. USB pins **not connected**. |
| 4 | 2× USB-A | Both from CM5 USB 3.0 ports (5 Gb/s, simultaneous) + per-port ESD |
| 5 | USB-C programming | CM5 USB 2.0 → rpiboot / eMMC flashing |
| 6 | RTC + battery | I²C RTC + CR2032 coin cell |
| 7 | 40-pin GPIO header | Standard Pi HAT pinout, 3.3 V Vref |
| 8 | 14-pin header | Exact CM5IO **J2** pinout (see §4) |
| 9 | Debug UART | 3-pin header (GND / TX / RX) |
| 10 | **GPS connector** | PPS + UART(TX/RX) + 3.3 V + GND. Powers + reads a GPS module. |
| 11 | **PPS distribution** | GPS PPS → TVS → Schmitt buffer → fan-out: CM5 SYNC + 2 header taps (UWB, spare/scope). Board is always a PPS **sink** (GPS-sourced). |
| 12 | **M.2 E-key target** | AsiaRF AW7915 (MT7915). 3.3 V rail sized for it (see §5). |
| — | Omitted | microSD, M.2 M-key/NVMe, MIPI DSI/CSI, HDMI, PoE, PPS source/SMA |
**Module requirement:** standard **eMMC CM5** (not Lite) — no microSD or other boot storage on board.
---
## 3. CM5 resource allocation (no contention)
| CM5 resource | Destination |
|--------------|-------------|
| BCM54210PE GbE PHY | RJ45 magjack |
| PCIe ×1 Gen2 | M.2 E-key (Wi-Fi) |
| USB 2.0 HS | USB-C (programming) |
| USB 3.0 #1 | USB-A #1 |
| USB 3.0 #2 | USB-A #2 |
| Debug UART | 3-pin header |
| GPIO UART (NMEA) | GPS connector — time-of-day from GPS |
| SYNC (IEEE 1588) in | PPS distribution block ← GPS PPS (buffered) |
| GPIO ×~26 | 40-pin header (+ NMEA UART + select lines) |
Every interface lands on its own dedicated connector. The only resource with a historical conflict (USB 2.0) is cleanly assigned to programming, since Bluetooth was dropped (Wi-Fi-only E-key).
---
## 4. 14-pin header — CM5IO J2 reference pinout
| Pin | Function | Notes |
|-----|----------|-------|
| 1–2 | nRPIBOOT | Jumper → boot from USB (recovery/flash) |
| 3–4 | EEPROM_nWP | Write-protect CM5 EEPROM |
| 6 | SYNC_OUT | IEEE 1588 timing; **bidirectional**, **3.3 V** (CM5 connector pin 18). Header pinout matches reference; the net is driven by the buffered PPS block (§5a). |
| 12 | PMIC_ENABLE | PMIC power control |
| 13–14 | Wake/shutdown | Push-button wake/shutdown |
Pins 5, 7–11 follow the reference (unassigned / ground). The **14-pin pinout matches CM5IO J2 exactly**, but the SYNC net (pin 6 ↔ CM5 connector pin 18) is **buffered + ESD-protected** at the PPS distribution block (§5a) and is **3.3 V** — no level translation needed (verified against `refs/CM5IO.kicad_sym`; see `CM5_Carrier_PinMap.md` correction C1).
---
## 5. Power architecture
Three regulators, **two independent 3.3 V rails** — the noisy Wi-Fi RF rail is isolated from the quiet rail that feeds GPS/IO and (critically) the PPS timing circuitry.
```
J_PWR (15V) ─► D_REV(ideal-diode FET) ─► VIN_PROT ─► [TVS] ─┬─► U_BUCK5 (15→5V, 5A) ─► +5V ─┬─► CM5 +5V
│ └─► USB VBUS sw ─► USB-A ×2
├─► U_BUCK33R (15→3.3V, 4A) ─► +3V3_RF ─► E-key (AW7915)
└─► U_BUCK33A (15→3.3V, 1A) ─► +3V3_AUX ─┬─► GPS module
├─► PPS Schmitt buffer (3V3, no translator)
├─► IO pull-ups / Vref side
└─► RTC domain
```
**Why two 3.3 V rails (not cascade):**
- The AW7915 pulls **3–3.5 A at 3.3 V (~11.5 W)** in bursty TX patterns. Putting that on its **own direct 15→3.3 buck** keeps the radio's switching/transient current off the 5 V/compute rail and off the quiet 3.3 V that feeds timing.
- **+3V3_AUX** is small (~1 A) and quiet — it powers the GPS module, the PPS Schmitt buffer, IO, and RTC. Isolating it from the RF rail protects PPS edge integrity (consistent with the hardened SYNC path).
- **+5V buck** now only carries CM5 + USB VBUS (not the reflected 3.3 V load), so it stays a clean 5 A part with a smaller inductor.
| Rail | Regulator | Vin | Current | Load |
|------|-----------|-----|---------|------|
| +5V | U_BUCK5 | 15 V | ≥5 A | CM5, USB VBUS, fan |
| +3V3_RF | U_BUCK33R | 15 V | 4 A | AW7915 (3–3.5 A) — direct, noise-isolated |
| +3V3_AUX | U_BUCK33A | 15 V | ~1 A | GPS, PPS buffer, IO, RTC — quiet rail |
| +VRTC | CR2032 / ORing | — | µA | CM5 RTC backup |
**Buck Vin rating:** all three bucks see 15 V nominal → spec parts rated **≥20 V** (covers 15 V + load-dump/transient margin). Note the 15→3.3 stages run ~22% duty — pick controllers comfortable with low duty cycle / high Vin (not 6 V-max commodity 5 V-input parts).
- **Reverse-polarity + reverse-current:** ideal-diode controller / ORing FET at the inlet (low drop vs a passive bridge — important at 15 V).
- **Bulk + inrush:** input bulk cap with soft-start; consider a hot-swap/inrush limiter if the 15 V source is shared or hot-plugged.
---
## 5a. PPS / timing distribution (hardened)
Board is always a **PPS sink** — GPS is the only source. Single clean input path, fanned out:
```
GPS PPS ─► [TVS/ESD] ─► [Schmitt buffer] ─┬─► CM5 SYNC (J2 pin-6 net, IEEE 1588 in)
├─► header tap 1 (UWB node)
└─► header tap 2 (spare / scope trigger)
```
- **GPS connector:** PPS, UART TX, UART RX, 3.3 V, GND (powers + reads the module). NMEA time-of-day comes in on a **40-pin GPIO UART**; PPS provides the precise edge.
- **Conditioning:** TVS + Schmitt (LVC1G17-class) — protects the CM5 pin and squares the edge for timestamp accuracy. (LVDS/comparator path noted as future if sub-ns distribution skew is ever needed.)
- **Fan-out:** low-skew buffer to CM5 + 2 header taps; keep tap stubs short and length-similar so the edge arrives coherently.
- **14-pin J2 stays exact** — SYNC still appears on J2 pin 6 per reference, but the *driven* PPS net originates from the buffered distribution block, not a raw off-board stub.
---
## 6. Layer stack & routing notes
- **4-layer** minimum. Controlled-impedance required for: PCIe ×1 (to E-key) and the 4 GbE MDI pairs (to magjack). 2-layer is not viable.
- Suggested stack: Sig / GND / PWR / Sig. Reference high-speed pairs to a solid plane.
- **PCIe:** CM5 has on-board AC-coupling on TX; RX coupling caps live on the card side (standard M.2). Length-match the pair; keep PERST/CLKREQ/REFCLK clean.
- **GbE:** 1:1 magjack, Bob-Smith termination, chassis-gap under the magjack; ESD array on the cable side.
- **USB3:** length-match SS pairs; ESD (USBLC6-class) on both A-ports.
- **DF40 placement:** copy the connector placement + keep-outs from the CM5IO KiCad files verbatim to de-risk the high-density interface.
---
## 7. BOM skeleton (per board)
| Block | Candidate parts | ~$/bd |
|-------|-----------------|-------|
| CM5 interface | 2× DF40C-100DS-0.4V (or matched) | 12–18 |
| Power inlet | ideal-diode ctrl (e.g. LM74700 / LTC4359-class) + TVS + FET | 1.5–3 |
| 15→5 V buck | sync buck 5 A (e.g. TPS5450/TPS56x-class) + L + caps | 2–4 |
| 3.3 V rail | **sync buck 4 A** (for AW7915) + L + caps | 2–4 |
| Ethernet | 1:1 GbE magjack + ESD array | 2–4 |
| M.2 E-key | E-key connector + standoff | 1.5–2 |
| PPS/GPS | Schmitt buffer + TVS + GPS conn (5-pin) + 2 tap headers | 1.5–3 |
| USB | 2× USB-A + 1× USB-C + 3× ESD arrays | 2–3.5 |
| RTC | I²C RTC + CR2032 holder + cell | 1–2 |
| Headers | 40-pin + 14-pin + 3-pin UART | 1–2 |
| Passives / misc | R/C/L, jumpers, LEDs, test points | 2–4 |
| **Per-board total** | | **~28–47** |
DF40 connectors dominate (~50–65 % of BOM). Everything else is commodity.
---
## 8. Cost estimate (turnkey PCBA, JLCPCB/PCBWay-class)
| Bucket | Qty 2 (build 5, use 2) | Qty 10 |
|--------|------------------------|--------|
| 4-layer ENIG fab | $30–60 | $40–85 |
| BOM | $90–145 | $185–290 |
| PCBA setup + placement | $55–95 | $85–150 |
| **Total** | **~$180–300** | **~$310–525** |
| **Per usable board** | ~$90–150 (of 2) | $31–53 |
Notes:
- Qty 2 is the worst unit price (all NRE, no volume break). Building 5 and keeping 3 spares is the smart prototype move — bring-up spares are cheap insurance.
- Qty 25–50 drops per-board 30–50 % as NRE amortizes and parts hit price breaks.
- DF40 connectors and the magjack are the items most likely to be consigned/special-order at a fab — check stock early.
- Budget for a **second spin**: mixed-signal (PCIe + power) rev-A boards rarely ship perfect.
---
## 9. Design → fab process
### Phase 0 — Setup
- Pull the **official CM5 design files (KiCad)** from Raspberry Pi (CM5IO is open hardware) — start point for connector placement, power, Ethernet.
- Confirm CM5 variant on the order line: **eMMC**, wireless optional (you may order **non-wireless** since the E-key card is your Wi-Fi).
- Pick the Wi-Fi card (e.g. AX210-class E-key) and verify driver support in your target distro/kernel.
### Phase 1 — Schematic capture
- Import CM5IO sheets; delete HDMI, MIPI, M-key, microSD, PoE blocks.
- Replace Type-C-power front-end with the **15 V inlet → ideal-diode → 5 A buck** block.
- Add **M.2 E-key** (PCIe + sidebands, USB pins NC), **2× USB-A** on USB3, **3.3 V** rail.
- Keep RTC, 40-pin, **J2 14-pin (exact)**, debug UART.
- ERC clean.
### Phase 2 — Layout
- Place DF40 connectors per reference; lock keep-outs and mounting holes.
- Define 4-layer stack + impedance targets (PCIe ~85–90 Ω diff, USB3 ~90 Ω, Ethernet ~100 Ω).
- Route high-speed first (PCIe, GbE, USB3), then power, then GPIO/headers.
- DRC + impedance check; back-check against CM5 datasheet track-length guidance.
### Phase 3 — Prototype fab (build 5, use 2)
- 4-layer, ENIG, turnkey PCBA. Confirm part availability before order (DF40, magjack).
- Lead time ~1–2 weeks fab+assembly typical.
### Phase 4 — Bring-up
- Power-rail checkout (no module): verify 5 V/3.3 V, reverse-polarity behavior, inrush.
- Insert CM5; confirm boot, rpiboot via USB-C, eMMC flash.
- Verify GbE link + (if needed) 1588/SYNC on J2 pin 6.
- Enumerate E-key Wi-Fi over PCIe; confirm driver loads.
- USB-A ports: link + storage throughput (~400–450 MB/s expected on USB3 Gen1).
- RTC hold-over test.
### Phase 5 — Rev B + production
- Fold bring-up fixes (expect at least one spin).
- SYNC buffering resolved (Schmitt + series R, 3.3 V) — verify PPS edge/jitter at bring-up.
- Scale to qty 25–50 for unit-cost drop.
---
## 10. Open / future decisions (parked)
- **SYNC buffering:** RESOLVED — buffered (Schmitt + TVS), GPS-sourced sink, 2 fan-out taps. See §5a.
- **Wi-Fi card:** AW7915 (MT7915) named target; bench-validation in progress (4-addr/AP/bridge modes, real 3.3 V draw). Confirm mt76 mode support before committing rev A.
- **3.3 V buck:** sized 4 A for AW7915; confirm against the *specific* AW7915 variant (2T2R 3 A vs 4T4R 3.5 A) once bench numbers are in.
- **Storage:** none on board; USB-A sockets + external SSD (~450 MB/s, same as native lane ceiling).
- **15 V inlet connector:** barrel jack vs locking 2-pin — pick at layout.
- **UWB sync (function 2):** no rev-A PCB change — Arduino+UWB couples via USB / 40-pin GPIO; references the PPS header tap. Revisit only if a dedicated UWB interface is wanted later.
- **PPS distribution skew:** Schmitt is fine for 1PPS; LVDS/comparator path is the upgrade if sub-ns inter-node skew ever matters.
- **Enclosure / mounting:** not yet specified.

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# CM5 Carrier — Authoritative Pin Map (CM5 ↔ Carrier Nets)
**Source of truth:** `refs/CM5IO.kicad_sym`, symbol `ComputeModule5-CM5` (official Raspberry Pi CM5 IO Board rev 2 KiCad files). All 200 connector pins parsed directly from the symbol — these are the real pin numbers a layout engineer maps to.
**Connector model:** the CM5 mates via two 100-pin Hirose DF40 connectors. In the symbol, pins **1–100** are one connector strip and **101–200** the other. KiCad resolves the physical split from the footprint; the pin *numbers* below are what the netlist uses.
Companion to `CM5_Carrier_Design.md` and `CM5_Carrier_Pinout_BOM.md`. **This file supersedes** the "by datasheet net name" placeholders in those docs.
---
## 0. Corrections found during pin verification (read first)
Mapping the real symbol exposed three errors in the earlier `CM5_Carrier_Pinout_BOM.md`:
| # | Prior doc said | Reality (from symbol) | Impact |
|---|----------------|------------------------|--------|
| **C1** | CM5 SYNC is **1.8 V**, needs a 3V3→1V8 level translator (SN74LVC1T45) on the PPS path | Pin 18 is **`Ethernet_SYNC_OUT(3.3v)`** — 3.3 V signalling | **Delete the level translator (U_LVLSHIFT).** 3.3 V GPS PPS → Schmitt → drives pin 18 directly. Removes a part and a gotcha. |
| **C2** | Debug UART uses "dedicated debug pins on the DF40"; NMEA GPS can take GPIO14/15 (UART0) | **No dedicated debug-UART pins exist.** The only console UART is GPIO14/15 (UART0). Reference board has no debug-UART connector. | **Conflict.** Keep debug console on GPIO14/15; **move NMEA GPS to UART2 (GPIO4/5).** |
| **C3** | Fan is "optional, keep from ref" with no pin assignment | Dedicated **`FAN_PWM` (pin 19)** + **`FAN_TACHO` (pin 16)** exist | Fan header wires to pins 19/16, not GPIO. |
Also confirmed useful: CM5 **sources** `+3.3V` (pins 84/86) and `+1.8V` (88/90); there's a dedicated `VBAT` (76) for RTC backup, and `GPIO_VREF` (78) **must be driven** to set the GPIO bank level.
---
## 1. Power & control pins
| CM5 pin(s) | Net | Direction | Carrier connection |
|-----------|-----|-----------|--------------------|
| 77, 79, 81, 83, 85, 87 | `+5v_(Input)` | **in** to CM5 | **+5V** from `U_BUCK5` (main module supply). Decouple per datasheet; all 6 pins tied. |
| 84, 86 | `+3.3v_(Output)` | out of CM5 | CM5-sourced 3.3 V (limited current). Usable for `GPIO_VREF`, light pull-ups. **Do not** power the AW7915 from this. |
| 88, 90 | `+1.8v_(Output)` | out of CM5 | CM5-sourced 1.8 V. Spare; route to a test point. |
| 78 | `GPIO_VREF(1.8v/3.3v_Input)` | **in** to CM5 | **Tie to 3.3 V** (from CM5 `+3.3v` out or `+3V3_AUX`) to set the 40-pin bank to 3.3 V logic. |
| 76 | `VBAT` | **in** to CM5 | RTC backup: CR2032 (BT1) via ORing/diode. |
| 99 | `PMIC_ENABLE` | in | → J2 pin 12. Power enable/disable. |
| 92 | `PWR_BUT` | in | → J2 pin 13 wake/shutdown push-button. |
| 93 | `nRPIBOOT` | in | → J2 pin 1 jumper **and** boot-select for USB-C rpiboot. |
| 20 | `EEPROM_nWP` | in | → J2 pin 3 EEPROM write-protect jumper. |
| 95 | `LED_nPWR` | out | Power LED (sink). |
| 21 | `LED_nACT` | out | Activity LED (sink). |
| 111 | `VBUS_EN` | out | USB host VBUS enable → gates USB-A VBUS load switch. |
| 94 / 96 | `CC1` / `CC2` | — | Module USB-C CC lines. **See §6 note** — our USB-C is data/rpiboot only; verify against reference wiring. |
| 1,2,7,8,13,14,22,23,32,33,42,43,52,53,59,60,65,66,71,74,98,107,108,113,114,119,120,125,126,131,132,137,138,144,150,155,156,161,162,167,168,173,174,179,180,185,186,191,192,197,198 | `GND` (51 pins) | — | Stitch to ground plane. |
---
## 2. Ethernet (CM5 on-module BCM54210PE → magjack)
No external PHY. 1:1 magjack + ESD. 100 Ω diff pairs.
| CM5 pin | Net | Magjack |
|---------|-----|---------|
| 12 / 10 | `Ethernet_Pair0_P` / `_N` | MDI0 ± |
| 4 / 6 | `Ethernet_Pair1_P` / `_N` | MDI1 ± |
| 11 / 9 | `Ethernet_Pair2_P` / `_N` | MDI2 ± |
| 3 / 5 | `Ethernet_Pair3_P` / `_N` | MDI3 ± |
| 17 | `Ethernet_nLED2(3.3v)` | Link/activity LED |
| 15 | `Ethernet_nLED3(3.3v)` | Speed LED |
| **18** | **`Ethernet_SYNC_OUT(3.3v)`** | **IEEE 1588 timing — 3.3 V, bidirectional → PPS block (see §5)** |
Magjack PoE center-tap pins: **NC** (no PoE). Bob-Smith termination + ESD array on cable side.
---
## 3. PCIe ×1 Gen2 → M.2 E-key (Wi-Fi, AW7915)
| CM5 pin | Net | E-key |
|---------|-----|-------|
| 110 / 112 | `PCIe_CLK_P` / `_N` | REFCLK ± (100 MHz) |
| 116 / 118 | `PCIe_RX_P` / `_N` | card→host (PER ±). **AC-couple caps on carrier.** |
| 122 / 124 | `PCIe_TX_P` / `_N` | host→card (PET ±). AC-coupled on CM5 side. |
| 109 | `PCIe_nRST` | PERST# |
| 102 | `PCIe_nCLKREQ` | CLKREQ# |
| 104 | `PCIE_nWAKE` | PEWAKE# (optional; pull-up) |
| 106 | `PCIE_PWR_EN` | gate for E-key 3.3 V enable (optional) |
E-key 3.3 V (W_DISABLE rail / VCC) ← **`+3V3_RF`** (dedicated 15→3.3 V 4 A buck). E-key USB pins **NC** (Wi-Fi only, no BT). PCIe pairs ~85 Ω diff; length-match; REFCLK matched pair.
---
## 4. USB
| CM5 pins | Net | Goes to |
|----------|-----|---------|
| 130/128, 142/140, 134/136 | `USB3-0-RX_P/N`, `USB3-0-TX_P/N`, `USB3-0-D_P/N` | **USB-A #1** (SS RX/TX pairs + USB2 D±) |
| 159/157, 171/169, 163/165 | `USB3-1-RX_P/N`, `USB3-1-TX_P/N`, `USB3-1-D_P/N` | **USB-A #2** |
| 105 / 103 | `USB2_P` / `USB2_N` | **USB-C** (rpiboot/programming) |
| 101 | `USB_OTG_ID` | USB-C OTG ID (or NC/strap for device mode) |
USB-A VBUS via current-limit load switch gated by `VBUS_EN` (pin 111). ESD (USBLC6-class) on each external port. SS pairs ~90 Ω diff.
---
## 5. PPS / timing distribution (corrected — no level shifter)
Board is a **PPS sink**; GPS is the only source. **SYNC is 3.3 V** (pin 18) so the path is all-3.3 V:
```
J_GPS.PPS (3V3) ─► [TVS] ─► [Schmitt LVC1G17, 3V3] ─► PPS_CLEAN(3V3) ─┬─► [Rs] ─► CM5 pin 18 (Ethernet_SYNC_OUT, cfg as input)
├─► J_PPS1 (UWB tap)
└─► J_PPS2 (scope/spare tap)
```
- **No 3V3→1V8 translator** (correction C1). Delete `U_LVLSHIFT` / SN74LVC1T45 from the BOM.
- Add a small **series resistor `Rs`** (e.g. 33–100 Ω) between the Schmitt output and pin 18: pin 18 is bidirectional, so Rs prevents a driver fight if firmware ever configures it as output. Board config is always input.
- Schmitt + TVS still wanted: square the off-board GPS edge, protect the pin.
| Net | From | To | Level |
|-----|------|----|-------|
| `GPS_PPS_RAW` | J_GPS.1 | TVS → Schmitt in | 3.3 V |
| `PPS_CLEAN` | Schmitt out | fan-out ×3 | 3.3 V |
| `PPS_SYNC` | via Rs | CM5 pin 18 | 3.3 V |
| `NMEA_TX` | CM5 GPIO4 (UART2 TX) | J_GPS.RX | 3.3 V |
| `NMEA_RX` | CM5 GPIO5 (UART2 RX) | J_GPS.TX | 3.3 V |
---
## 6. UART assignments (corrected — C2)
There is **one console UART** on GPIO14/15 and no dedicated debug pins. So:
| Function | CM5 UART | GPIO (BCM) | CM5 pins | 40-pin header | Connector |
|----------|----------|-----------|----------|---------------|-----------|
| **Debug console** | UART0 | GPIO14 (TXD0) / GPIO15 (RXD0) | 55 / 51 | pins 8 / 10 | J_UART (3-pin tap) |
| **NMEA GPS** | UART2 | GPIO4 / GPIO5 | 54 / 34 | pins 7 / 29 | J_GPS (via dtoverlay `uart2`) |
NMEA on UART2 keeps the console free. GPIO4/5 still appear on the 40-pin (shared net) — document that pins 7/29 are committed to GPS when fitted. PPS edge does **not** use a UART — it's the dedicated SYNC pin 18.
> USB-C CC note: the module exposes `CC1`/`CC2` (pins 94/96). Our USB-C is data-only for rpiboot; put 5.1 kΩ pulldowns at the USB-C connector for UFP/sink detection. Before finalizing, check how `refs/CM5IO.kicad_sch` ties module CC1/CC2 (the reference uses USB-C as a power path; we don't) — likely leave module CC pins per reference or NC.
---
## 7. 40-pin GPIO header — CM5 pin behind each BCM GPIO
The 40-pin positions are standard (see `CM5_Carrier_Pinout_BOM.md` §2). This table gives the **CM5 connector pin** behind each GPIO so the layout can route header→module directly.
| BCM | CM5 pin | 40-pin pos | Alt / use here |
|-----|---------|-----------|----------------|
| GPIO2 | 58 | 3 | I2C1 SDA |
| GPIO3 | 56 | 5 | I2C1 SCL |
| GPIO4 | 54 | 7 | **UART2 TX → NMEA** |
| GPIO5 | 34 | 29 | **UART2 RX → NMEA** |
| GPIO6 | 30 | 31 | |
| GPIO7 | 37 | 26 | SPI0 CE1 |
| GPIO8 | 39 | 24 | SPI0 CE0 |
| GPIO9 | 40 | 21 | SPI0 MISO |
| GPIO10 | 44 | 19 | SPI0 MOSI |
| GPIO11 | 38 | 23 | SPI0 SCLK |
| GPIO12 | 31 | 32 | PWM0 |
| GPIO13 | 28 | 33 | PWM1 |
| GPIO14 | 55 | 8 | **UART0 TXD → debug** |
| GPIO15 | 51 | 10 | **UART0 RXD → debug** |
| GPIO16 | 29 | 36 | |
| GPIO17 | 50 | 11 | |
| GPIO18 | 49 | 12 | PCM_CLK |
| GPIO19 | 26 | 35 | PCM_FS |
| GPIO20 | 27 | 38 | PCM_DIN |
| GPIO21 | 25 | 40 | PCM_DOUT |
| GPIO22 | 46 | 15 | |
| GPIO23 | 47 | 16 | |
| GPIO24 | 45 | 18 | |
| GPIO25 | 41 | 22 | |
| GPIO26 | 24 | 37 | |
| GPIO27 | 48 | 13 | |
| ID_SD (GPIO0) | 36 | 27 | HAT EEPROM I2C0 SDA |
| ID_SC (GPIO1) | 35 | 28 | HAT EEPROM I2C0 SCL |
Other I²C: `SCL0`/`SDA0` (pins 80/82) = I2C0 (camera/HAT-ID domain); `CAM_GPIO0`/`1` (97/100) — route to test points or leave NC (no camera).
---
## 8. Fan, radio-disable, RTC
| CM5 pin | Net | Use |
|---------|-----|-----|
| 19 | `FAN_PWM` | → J_FAN PWM (dedicated, not GPIO) |
| 16 | `FAN_TACHO` | → J_FAN tach |
| 89 | `WiFi_nDisable` | If a **wireless** CM5 is fitted, tie low to disable onboard radio (E-key is our Wi-Fi). With non-wireless CM5: NC. Mirrors ref J3. |
| 91 | `BT_nDisable` | As above for BT. |
| 76 | `VBAT` | CR2032 (BT1) → CM5 on-module RTC backup |
CM5 has an **on-module RTC** — the carrier only supplies the backup cell on `VBAT`. No external I²C RTC needed (drop the optional PCF85063A mention).
---
## 9. Explicitly unused / NC pin groups
Deleted features — leave these CM5 pins **No-Connect**:
| Group | CM5 pins | Why NC |
|-------|----------|--------|
| HDMI0/HDMI1 | 143,145,146,147,148,149,151,152,153,154,158,160,164,166,170,172,176,178,182,184,188,190,199,200 | No display out |
| MIPI0 (DSI/CSI) | 115,117,121,123,127,129,133,135,139,141 | No display/camera |
| MIPI1 (DSI/CSI) | 175,177,181,183,187,189,193,194,195,196 | No display/camera |
| microSD | 57,61,62,63,64,67,68,69,70,72 (SD_*) + 73 (`SD_VDD_Override`), 75 (`SD_PWR_ON`) | eMMC module; no SD card |
> If a **camera** is ever wanted, MIPI0 (pins 115–141) is the block to revive — flagged in design doc as the only realistic add-back.
---
## 10. What changed in the companion docs
Apply these so all three files agree (done in markdown; the **`.xlsx` BOM still lists `U_LVLSHIFT` and should drop it**):
- `CM5_Carrier_Pinout_BOM.md` §3, §6, §12: SYNC is 3.3 V; remove level-shifter; PPS drives pin 18 via series R.
- NMEA moved to UART2 (GPIO4/5); debug stays UART0 (GPIO14/15).
- Add FAN_PWM/TACHO (pins 19/16) to the fan header net.
- BOM: **delete line 15 (U_LVLSHIFT, SN74LVC1T45)**; add one 0402 series R on PPS→SYNC.
</content>
</invoke>

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# CM5 Carrier — Pinouts, Nets & BOM
Companion to `CM5_Carrier_Design.md`. This is the schematic-capture worksheet: connector pinouts, the net list grouped by interface, and a BOM with candidate MPNs.
> **Sourcing note on CM5 ball/pin numbers:** the two 100-pin connectors (J1 = pins 1–100 top, J2mod = pins 101–200 bottom) carry every CM5 signal. Rather than transcribe 200 pins (error-prone), this sheet references CM5 signals by their **datasheet net names**; pull exact pin numbers from the official CM5 KiCad symbol when capturing. All *user-facing* connector pinouts (40-pin, 14-pin J2, USB, GPS, PPS, UART) are given exactly. The 40-pin map below is verified against the CM5/Pi-5 standard.
---
## 1. Connector inventory & reference designators
| RefDes | Connector | Notes |
|--------|-----------|-------|
| J1 / J2MOD | 2× 100-pin DF40 (to CM5) | Hirose DF40C-100DS-0.4V mate; 1.5/2.0/4.0 mm stack options |
| J_PWR | 15 VDC input | barrel jack or 2-pin locking |
| J_ETH | RJ45 magjack (GbE) | 1:1, integrated magnetics |
| J_E | M.2 E-key socket (2230) | Wi-Fi (AW7915) |
| J_USB1 | USB-A (USB3) | |
| J_USB2 | USB-A (USB3) | |
| J_UPROG | USB-C | rpiboot/programming |
| J_GPIO | 40-pin 2.54 mm header | Pi HAT |
| J2 | 14-pin 2.54 mm header | CM5IO J2 reference |
| J_UART | 3-pin header | debug UART |
| J_GPS | 5-pin header | PPS+UART+3V3+GND |
| J_PPS1 | 2-pin header | PPS tap → UWB |
| J_PPS2 | 2-pin header | PPS tap → scope/spare |
| BT1 | CR2032 holder | RTC backup |
| J_FAN | 4-pin JST-SH | PWM fan (optional, keep from ref) |
---
## 2. 40-pin GPIO header (J_GPIO) — exact pinout
Standard Raspberry Pi / CM5 HAT pinout. **BCM GPIO** numbering.
| Pin | Signal | | Pin | Signal |
|-----|--------|--|-----|--------|
| 1 | 3V3 | | 2 | 5V |
| 3 | GPIO2 (SDA1) | | 4 | 5V |
| 5 | GPIO3 (SCL1) | | 6 | GND |
| 7 | GPIO4 (GPCLK0) | | 8 | GPIO14 (TXD0) |
| 9 | GND | | 10 | GPIO15 (RXD0) |
| 11 | GPIO17 | | 12 | GPIO18 (PCM_CLK) |
| 13 | GPIO27 | | 14 | GND |
| 15 | GPIO22 | | 16 | GPIO23 |
| 17 | 3V3 | | 18 | GPIO24 |
| 19 | GPIO10 (MOSI) | | 20 | GND |
| 21 | GPIO9 (MISO) | | 22 | GPIO25 |
| 23 | GPIO11 (SCLK) | | 24 | GPIO8 (CE0) |
| 25 | GND | | 26 | GPIO7 (CE1) |
| 27 | GPIO0 (ID_SD) | | 28 | GPIO1 (ID_SC) |
| 29 | GPIO5 | | 30 | GND |
| 31 | GPIO6 | | 32 | GPIO12 (PWM0) |
| 33 | GPIO13 (PWM1) | | 34 | GND |
| 35 | GPIO19 (PCM_FS) | | 36 | GPIO16 |
| 37 | GPIO26 | | 38 | GPIO20 (PCM_DIN) |
| 39 | GND | | 40 | GPIO21 (PCM_DOUT) |
**NMEA UART assignment (CORRECTED):** use **UART2** on GPIO4 (pin 7) / GPIO5 (pin 29) → cross to GPS RX/TX on J_GPS, enabled via `dtoverlay=uart2`. The **debug console keeps UART0** (GPIO14/15, pins 8/10) — there are no dedicated debug-UART pins on the CM5 connector (correction C2). Pins 7/29 are committed to GPS when J_GPS is fitted.
**Vref:** Pin 1/17 3V3 sets HAT logic level. CM5 GPIO bank is 3.3 V by default (R5 fitted equivalent); do not feed 1.8 V unless a deliberate Vref change is made on the module side.
---
## 3. 14-pin header (J2) — exact CM5IO reference
| Pin | Net | Function |
|-----|-----|----------|
| 1 | nRPIBOOT | jumper 1–2 → boot from USB |
| 2 | GND | |
| 3 | EEPROM_nWP | jumper 3–4 → write-protect EEPROM |
| 4 | GND | |
| 5 | NC | (reference: unassigned) |
| 6 | **SYNC** | IEEE 1588 timing — driven by PPS dist block (input to CM5). Maps to CM5 pin 18 `Ethernet_SYNC_OUT`, **3.3 V**. |
| 7 | NC | |
| 8 | NC | |
| 9 | NC | |
| 10 | NC | |
| 11 | NC | |
| 12 | PMIC_ENABLE | power enable/disable |
| 13 | BUTTON (wake/shutdown) | push-button |
| 14 | GND | button return |
> **CORRECTED (per `refs/CM5IO.kicad_sym`):** the CM5 timing pin is a single **`Ethernet_SYNC_OUT` on connector pin 18, at 3.3 V**, bidirectional (configurable as input). There is no separate 1.8 V SYNC_IN. **No level translation is needed** — the 3.3 V GPS PPS drives it directly through the Schmitt + a series R. See `CM5_Carrier_PinMap.md` §5 and correction C1.
---
## 4. M.2 E-key (J_E) — net assignment (Wi-Fi only, AW7915)
A+E key edge. Populate PCIe + control; leave USB pins NC.
| M.2 pin(s) | Net | To |
|------------|-----|-----|
| 32, 34 (PERST0#, etc.) | PCIE_PERST# | CM5 PCIe PERST |
| CLKREQ0# | PCIE_CLKREQ# | CM5 PCIe CLKREQ |
| REFCLK+ / REFCLK− | PCIE_REFCLK_P/N | CM5 PCIe refclk (100 MHz) |
| PETp0/PETn0 | PCIE_TX_P/N | CM5 PCIe TX (AC-coupled on CM5) |
| PERp0/PERn0 | PCIE_RX_P/N | CM5 PCIe RX (AC-couple caps on carrier) |
| W_DISABLE1# (RF_KILL) | WIFI_DISABLE# | pull-up + optional GPIO |
| 3.3 V pins | +3V3_RF | from 15→3.3 V 4 A RF buck (direct) |
| GND | GND | |
| USB D+/D− (E-key) | **NC** | Bluetooth not used |
PCIe pair impedance ~85 Ω diff. Keep REFCLK as a matched pair; series-couple per M.2 spec.
---
## 5. USB assignments
| Port | CM5 source net | ESD |
|------|----------------|-----|
| J_USB1 (USB-A) | USB3_0 (SS pairs + USB2 D±) | USBLC6-2SC6 |
| J_USB2 (USB-A) | USB3_1 (SS pairs + USB2 D±) | USBLC6-2SC6 |
| J_UPROG (USB-C) | USB2_0 (D±) + CC1/CC2 5.1k | USBLC6-2SC6 |
- USB-C is **device/programming** (rpiboot): wire D± to CM5 USB 2.0 port; CC1/CC2 each get 5.1 kΩ to GND (sink/UFP). Pair with nRPIBOOT jumper on J2.
- USB-A SuperSpeed pairs ~90 Ω diff; USB2 D± ~90 Ω diff.
- VBUS to USB-A from 5 V via current-limit switch (~0.9–1.2 A/port).
---
## 6. PPS / timing distribution — nets
```
J_GPS.PPS (3V3) ─► [TVS] ─► [Schmitt LVC1G17, 3V3] ─► PPS_CLEAN(3V3) ─┬─► [Rs 33–100Ω] ─► CM5 pin 18 (SYNC, 3V3, cfg input)
├─► J_PPS1 (UWB tap, 3V3)
└─► J_PPS2 (scope tap, 3V3)
```
| Net | From | To | Level |
|-----|------|----|-------|
| GPS_PPS_RAW | J_GPS.1 | TVS → Schmitt in | 3.3 V |
| PPS_CLEAN | Schmitt out | fan-out (3 loads) | 3.3 V |
| PPS_SYNC | via Rs | CM5 pin 18 (SYNC) | **3.3 V** |
| NMEA_TX | CM5 GPIO4 (UART2 TX, pin 7) | J_GPS.RX | 3.3 V |
| NMEA_RX | CM5 GPIO5 (UART2 RX, pin 29) | J_GPS.TX | 3.3 V |
**Corrected detail:** CM5 SYNC (pin 18) is **3.3 V** — no level translation. The Schmitt squares the off-board GPS edge and the series Rs guards against a driver fight (pin 18 is bidirectional; board always configures it as input). PPS_CLEAN feeds all three loads at 3.3 V. **NMEA moved to UART2 (GPIO4/5)** so the debug console keeps UART0 (GPIO14/15) — see correction C2 in `CM5_Carrier_PinMap.md`.
### J_GPS (5-pin) pinout
| Pin | Net |
|-----|-----|
| 1 | PPS (in, 3V3) |
| 2 | NMEA_RX ← GPS TX (CM5 GPIO5 / UART2 RX, pin 29) |
| 3 | NMEA_TX → GPS RX (CM5 GPIO4 / UART2 TX, pin 7) |
| 4 | +3V3_AUX (out, to power module) |
| 5 | GND |
### J_PPS1 / J_PPS2 (2-pin each)
| Pin | Net |
|-----|-----|
| 1 | PPS_CLEAN (3V3) |
| 2 | GND |
---
## 7. Power tree — nets
```
J_PWR (15V) ─► D_REV(ideal-diode FET) ─► VIN_PROT ─► [TVS]
VIN_PROT ─► U_BUCK5 (15→5V, 5A) ─► +5V ─┬─► CM5 +5V (J1 5V input pins)
└─► USB VBUS switch ─► USB-A ×2
VIN_PROT ─► U_BUCK33R (15→3.3V, 4A) ─► +3V3_RF ─► E-key (AW7915) [direct, noise-isolated]
VIN_PROT ─► U_BUCK33A (15→3.3V, 1A) ─► +3V3_AUX ─┬─► GPS module
├─► PPS Schmitt buffer (3V3)
├─► IO pull-ups
└─► RTC domain
```
| Rail | Source | Current | Load |
|------|--------|---------|------|
| VIN_PROT | 15 V via ideal-diode | board total | buck inputs |
| +5V | U_BUCK5 | ≥5 A | CM5, USB VBUS, fan |
| +3V3_RF | U_BUCK33R (direct 15→3.3) | 4 A | AW7915 (3–3.5 A) — isolated RF rail |
| +3V3_AUX | U_BUCK33A (direct 15→3.3) | ~1 A | GPS, PPS buffer, IO, RTC — quiet rail |
| +VRTC | CR2032 / +3V3_AUX ORing | µA | CM5 RTC domain |
All three bucks see 15 V → rate ≥20 V. The 15→3.3 stages run ~22% duty; pick low-duty-capable controllers.
CM5 +5 V input lands on the DF40 **+5V (input)** pins (per 40-pin ref: pins 77/79/81/83 are +5V on the HAT; the module 5 V input is on the DF40 power pins — pull exact pins from KiCad).
---
## 8. Ethernet — nets (no external PHY)
CM5 BCM54210PE PHY pins (from DF40) → magjack. Per CM5 datasheet, a 1:1 magjack + ESD is all that's required.
| CM5 net | Magjack | Notes |
|---------|---------|-------|
| ETH_PAIR0_P/N | TX+/− (or MDI0) | 100 Ω diff |
| ETH_PAIR1_P/N | MDI1 | |
| ETH_PAIR2_P/N | MDI2 | |
| ETH_PAIR3_P/N | MDI3 | gigabit uses all 4 |
| ETH_nLED1/2/3 | jack LEDs (3V3) | activity/link |
| Bob-Smith term + ESD | cable side | TVS array, 75 Ω + 1 nF terms |
PoE pins of the magjack: leave **unloaded / NC** (no PoE in this design).
---
## 9. RTC
| Net | Part | Notes |
|-----|------|-------|
| RTC_SDA/SCL | CM5 I2C (dedicated RTC I2C on CM5) | CM5 has internal RTC; carrier provides battery backup |
| +VRTC | CR2032 via BT1 | back-up to CM5 RTC battery pin |
> CM5 has an **on-module RTC**; the carrier mainly provides the **CR2032 backup cell** to the CM5 RTC battery input (per CM5IO reference). If an *external* I²C RTC is also wanted (redundancy), add e.g. PCF85063A on a GPIO I²C — optional, default is just the coin cell to CM5.
---
## 10. Bill of Materials (per board) — candidate MPNs
| # | RefDes | Qty | Description | Candidate MPN | ~$ |
|---|--------|-----|-------------|---------------|-----|
| 1 | J1,J2MOD | 2 | 100-pin DF40 0.4 mm receptacle | Hirose DF40C-100DS-0.4V(51) | 12–18 |
| 2 | U_BUCK5 | 1 | Sync buck 15→5 V, ≥5 A (≥20 V Vin) | TI TPS54560 / MPS MP2316 | 1.5–3 |
| 3 | U_BUCK33R | 1 | Sync buck **15→3.3 V, 4 A** (RF rail, ≥20 V Vin, low-duty) | TI TPS54424 / MPS MP2143 | 1–2 |
| 3b | U_BUCK33A | 1 | Sync buck **15→3.3 V, 1 A** (AUX/quiet rail, ≥20 V Vin) | TI TPS54202 / MPS MP2459 | 0.5–1.2 |
| 4 | D_REV | 1 | Ideal-diode/reverse-polarity ctrl + FET | TI LM74700-Q1 + CSD18xx FET | 1.2–2.5 |
| 5 | TVS_IN | 1 | TVS, >15 V standoff (e.g. 18 V) | SMBJ18A | 0.2 |
| 6 | J_ETH | 1 | RJ45 1:1 GbE magjack | Pulse JXD0-0001NL / Bel V890-1AX | 2–4 |
| 7 | ESD_ETH | 1 | Ethernet ESD array | TI TPD4E1U06 / Bourns | 0.3–0.6 |
| 8 | J_E | 1 | M.2 E-key (A+E) 2230 conn + standoff | Amphenol/Attend 119A-92A00 | 1.2–2 |
| 9 | C_PCIE | 4 | PCIe RX AC-couple 0.1 µF | GRM 0402 100 nF | 0.05 |
| 10 | J_USB1/2 | 2 | USB-A USB3.0 right-angle | Amphenol UE27AC54100 | 0.8–1.4 ea |
| 11 | J_UPROG | 1 | USB-C 16-pin (USB2 + CC) | GCT USB4085 | 0.5–1 |
| 12 | ESD_USB | 3 | USB ESD array | ST USBLC6-2SC6 | 0.15 ea |
| 13 | U_VBUS | 1 | USB VBUS current-limit switch | TI TPS2552 / AP22653 | 0.5–1 |
| 14 | U_SCHMITT | 1 | Single Schmitt buffer 3V3 | TI SN74LVC1G17 | 0.1 |
| 15 | ~~U_LVLSHIFT~~ | 0 | **REMOVED** — SYNC is 3.3 V, no translation needed (correction C1). Replace with one 0402 series R (in passives). | — | — |
| 16 | TVS_PPS | 1 | Low-cap TVS on PPS in | ESD9B / PESD | 0.1 |
| 17 | J_GPS | 1 | 5-pin 2.54 header | generic | 0.1 |
| 18 | J_PPS1/2 | 2 | 2-pin 2.54 header | generic | 0.05 ea |
| 19 | J_GPIO | 1 | 40-pin 2.54 dual header | generic | 0.5–0.8 |
| 20 | J2 | 1 | 14-pin 2.54 header | generic | 0.2 |
| 21 | J_UART | 1 | 3-pin 2.54 header | generic | 0.05 |
| 22 | BT1 | 1 | CR2032 holder + cell | Keystone 1058 + cell | 0.4–0.8 |
| 23 | J_PWR | 1 | 15 V barrel jack or 2-pin | CUI PJ-102AH | 0.4–0.8 |
| 24 | J_FAN | 1 | 4-pin JST-SH PWM fan → CM5 FAN_PWM (pin 19) + FAN_TACHO (pin 16) | JST SM04B-SRSS | 0.3 |
| 25 | — | ~60 | Passives (R/C/L), LEDs, TP, jumpers | 0402/0603 | 2–4 |
| | | | **Per-board BOM total** | | **~28–47** |
DF40 pair (line 1) = ~45–60% of BOM. Everything else commodity.
---
## 11. Net list summary (by interface)
| Interface | Nets | Endpoints |
|-----------|------|-----------|
| Power in | J_PWR, VIN_PROT, +5V, +3V3_RF, +3V3_AUX, +VRTC | J_PWR → D_REV → 3 bucks → CM5/E-key/IO |
| PCIe (E-key) | PCIE_TX_P/N, PCIE_RX_P/N, REFCLK_P/N, PERST#, CLKREQ#, W_DISABLE# | CM5 ↔ J_E |
| Ethernet | ETH_PAIR0-3_P/N, ETH_nLED1-3 | CM5 PHY ↔ J_ETH |
| USB3 #1 | USB3_0 SS±, USB2 D± | CM5 ↔ J_USB1 |
| USB3 #2 | USB3_1 SS±, USB2 D± | CM5 ↔ J_USB2 |
| USB2 prog | USB2_0 D±, CC1/CC2 | CM5 ↔ J_UPROG |
| PPS/timing | GPS_PPS_RAW, PPS_CLEAN, PPS_SYNC_18 | J_GPS → buffer → CM5 SYNC + J_PPS1/2 |
| NMEA UART | NMEA_TX, NMEA_RX | J_GPIO(14/15) ↔ J_GPS |
| Debug UART | DBG_TX, DBG_RX | CM5 debug UART ↔ J_UART |
| GPIO | GPIO0-27 | CM5 ↔ J_GPIO |
| Boot/ctrl | nRPIBOOT, EEPROM_nWP, PMIC_EN, BUTTON | CM5 ↔ J2 |
| RTC | +VRTC, RTC_SDA/SCL | BT1 → CM5 |
---
## 12. Schematic-capture checklist
1. Import CM5 KiCad symbol from `refs/CM5IO.kicad_sym` — pin map is now resolved in `CM5_Carrier_PinMap.md` (all 200 pins).
2. **SYNC (pin 18) is 3.3 V** — drive directly from the Schmitt via a series R; **no level translator** (corrected).
3. AC-couple PCIe **RX** on carrier (TX coupled on CM5).
4. CC 5.1 kΩ pulldowns on USB-C; nRPIBOOT jumper logic.
5. Magjack PoE pins NC; Bob-Smith + ESD on cable side.
6. Both 15→3.3 buck inductors/thermals sized for their rails (RF 4 A, AUX 1 A); all bucks rated ≥20 V Vin, low-duty-capable.
7. VBUS current-limit per USB-A port.
8. Confirm CM5 5 V input pin group and decoupling per datasheet.

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<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 1000 720" font-family="'DejaVu Sans Mono', monospace">
<defs>
<style>
.blk { fill:#10242b; stroke:#3fb6c4; stroke-width:1.6; rx:6; }
.cm5 { fill:#15323a; stroke:#5fd6e4; stroke-width:2.2; }
.pwr { fill:#2a1f12; stroke:#e0a83c; stroke-width:1.6; }
.conn { fill:#1a1326; stroke:#b07fe0; stroke-width:1.6; }
.lbl { fill:#dfeef0; font-size:13px; }
.sub { fill:#7fa6ad; font-size:10.5px; }
.plbl { fill:#f0d49a; font-size:13px; }
.clbl { fill:#d8c2f0; font-size:13px; }
.net { stroke:#3fb6c4; stroke-width:1.6; fill:none; }
.netp { stroke:#e0a83c; stroke-width:2.0; fill:none; }
.nettxt{ fill:#9fc4cb; font-size:10px; }
.title { fill:#eaf6f7; font-size:20px; font-weight:bold; }
.ttag { fill:#5fd6e4; font-size:11px; letter-spacing:2px; }
</style>
</defs>
<rect x="0" y="0" width="1000" height="720" fill="#0a181d"/>
<text x="40" y="46" class="ttag">CM5 CARRIER — FUNCTIONAL BLOCK DIAGRAM</text>
<text x="40" y="72" class="title">PTP-oriented compute node · GbE · Wi-Fi(E-key) · 15V in</text>
<!-- CM5 module (center) -->
<rect class="cm5" x="400" y="250" width="200" height="220" rx="8"/>
<text x="500" y="288" text-anchor="middle" class="lbl" font-size="16" font-weight="bold">CM5</text>
<text x="500" y="308" text-anchor="middle" class="sub">eMMC module</text>
<text x="500" y="322" text-anchor="middle" class="sub">(not Lite)</text>
<text x="500" y="346" text-anchor="middle" class="sub">BCM2712 · BCM54210PE PHY</text>
<line x1="420" y1="360" x2="580" y2="360" stroke="#2c4a52" stroke-width="1"/>
<text x="500" y="380" text-anchor="middle" class="sub">2× DF40 board-to-board</text>
<text x="500" y="396" text-anchor="middle" class="sub">PCIe x1 Gen2 · 1×USB2 · 2×USB3</text>
<text x="500" y="412" text-anchor="middle" class="sub">GbE PHY · 30×GPIO · SYNC(1588)</text>
<text x="500" y="428" text-anchor="middle" class="sub">debug UART</text>
<!-- POWER (top-left) -->
<rect class="pwr" x="40" y="110" width="150" height="64" rx="6"/>
<text x="115" y="138" text-anchor="middle" class="plbl">15 VDC IN</text>
<text x="115" y="156" text-anchor="middle" class="sub">jack / 2-pin</text>
<rect class="pwr" x="220" y="110" width="150" height="64" rx="6"/>
<text x="295" y="134" text-anchor="middle" class="plbl">Reverse-V</text>
<text x="295" y="150" text-anchor="middle" class="sub">ideal-diode FET</text>
<text x="295" y="164" text-anchor="middle" class="sub">+ TVS</text>
<rect class="pwr" x="400" y="110" width="150" height="64" rx="6"/>
<text x="475" y="134" text-anchor="middle" class="plbl">15→5V buck</text>
<text x="475" y="150" text-anchor="middle" class="sub">sync · 5A</text>
<text x="475" y="164" text-anchor="middle" class="sub">CM5 main rail</text>
<rect class="pwr" x="580" y="110" width="150" height="64" rx="6"/>
<text x="655" y="134" text-anchor="middle" class="plbl">3.3V buck 4A</text>
<text x="655" y="150" text-anchor="middle" class="sub">AW7915: 9W pk</text>
<text x="655" y="164" text-anchor="middle" class="sub">+ GPS + IO</text>
<path class="netp" d="M190,142 H220"/>
<path class="netp" d="M370,142 H400"/>
<path class="netp" d="M550,142 H580"/>
<path class="netp" d="M475,174 V210 H500 V250"/>
<text x="486" y="232" class="nettxt">5V</text>
<!-- ETHERNET (left) -->
<rect class="conn" x="40" y="250" width="150" height="64" rx="6"/>
<text x="115" y="274" text-anchor="middle" class="clbl">RJ45 magjack</text>
<text x="115" y="290" text-anchor="middle" class="sub">1:1 · GbE + ESD</text>
<text x="115" y="304" text-anchor="middle" class="sub">on-module PHY</text>
<path class="net" d="M400,300 H190"/>
<text x="250" y="294" class="nettxt">MDI 0-3 (4 pairs)</text>
<!-- M.2 E-KEY (left lower) -->
<rect class="conn" x="40" y="360" width="150" height="72" rx="6"/>
<text x="115" y="384" text-anchor="middle" class="clbl">M.2 E-key</text>
<text x="115" y="400" text-anchor="middle" class="sub">Wi-Fi card</text>
<text x="115" y="414" text-anchor="middle" class="sub">PCIe x1 · USB NC</text>
<text x="115" y="426" text-anchor="middle" class="sub">+ CLKREQ/PERST/RF_KILL</text>
<path class="net" d="M400,396 H190"/>
<text x="250" y="390" class="nettxt">PCIe x1 Gen2</text>
<!-- USB (right top) -->
<rect class="conn" x="810" y="200" width="150" height="58" rx="6"/>
<text x="885" y="224" text-anchor="middle" class="clbl">USB-A #1</text>
<text x="885" y="240" text-anchor="middle" class="sub">USB3 · 5Gb · +ESD</text>
<rect class="conn" x="810" y="272" width="150" height="58" rx="6"/>
<text x="885" y="296" text-anchor="middle" class="clbl">USB-A #2</text>
<text x="885" y="312" text-anchor="middle" class="sub">USB3 · 5Gb · +ESD</text>
<rect class="conn" x="810" y="344" width="150" height="58" rx="6"/>
<text x="885" y="364" text-anchor="middle" class="clbl">USB-C</text>
<text x="885" y="380" text-anchor="middle" class="sub">USB2 · rpiboot</text>
<text x="885" y="394" text-anchor="middle" class="sub">programming</text>
<path class="net" d="M600,300 H700 V229 H810"/>
<text x="640" y="294" class="nettxt">USB3 #1</text>
<path class="net" d="M600,320 H680 V301 H810"/>
<text x="640" y="334" class="nettxt">USB3 #2</text>
<path class="net" d="M600,340 H660 V373 H810"/>
<text x="640" y="356" class="nettxt">USB2</text>
<!-- HEADERS (bottom right cluster) -->
<rect class="conn" x="430" y="540" width="150" height="64" rx="6"/>
<text x="505" y="560" text-anchor="middle" class="clbl">40-pin GPIO</text>
<text x="505" y="576" text-anchor="middle" class="sub">Pi HAT · 3.3V Vref</text>
<text x="505" y="590" text-anchor="middle" class="sub">+ NMEA UART</text>
<rect class="conn" x="600" y="540" width="160" height="64" rx="6"/>
<text x="680" y="560" text-anchor="middle" class="clbl">14-pin (J2 ref)</text>
<text x="680" y="576" text-anchor="middle" class="sub">nRPIBOOT·EEPROM_nWP</text>
<text x="680" y="590" text-anchor="middle" class="sub">SYNC·PMIC_EN·wake</text>
<rect class="conn" x="780" y="455" width="150" height="58" rx="6"/>
<text x="855" y="479" text-anchor="middle" class="clbl">Debug UART</text>
<text x="855" y="495" text-anchor="middle" class="sub">3-pin GND/TX/RX</text>
<rect class="conn" x="780" y="540" width="150" height="64" rx="6"/>
<text x="855" y="564" text-anchor="middle" class="clbl">RTC + batt</text>
<text x="855" y="580" text-anchor="middle" class="sub">I²C · CR2032</text>
<path class="net" d="M470,470 V520 H505 V540"/>
<text x="476" y="514" class="nettxt">GPIO</text>
<path class="net" d="M540,470 V512 H680 V540"/>
<text x="600" y="506" class="nettxt">boot/SYNC/pwr</text>
<path class="net" d="M600,430 H855 V455"/>
<text x="700" y="424" class="nettxt">UART</text>
<path class="net" d="M580,448 H855 V540"/>
<text x="770" y="530" class="nettxt">I²C</text>
<!-- GPS + PPS distribution (lower left) -->
<rect class="conn" x="40" y="460" width="150" height="58" rx="6"/>
<text x="115" y="482" text-anchor="middle" class="clbl">GPS conn</text>
<text x="115" y="498" text-anchor="middle" class="sub">PPS+UART+3V3+GND</text>
<text x="115" y="510" text-anchor="middle" class="sub">powers module</text>
<rect class="blk" x="230" y="455" width="150" height="68" rx="6"/>
<text x="305" y="478" text-anchor="middle" class="lbl" font-size="12">PPS dist</text>
<text x="305" y="494" text-anchor="middle" class="sub">TVS + Schmitt</text>
<text x="305" y="508" text-anchor="middle" class="sub">sink only (GPS src)</text>
<path class="net" d="M190,489 H230"/>
<text x="196" y="483" class="nettxt">PPS</text>
<!-- PPS to CM5 SYNC -->
<path class="net" d="M380,472 H440 V470"/>
<text x="386" y="466" class="nettxt">→SYNC</text>
<!-- PPS fan-out taps -->
<rect class="conn" x="230" y="545" width="150" height="42" rx="6"/>
<text x="305" y="563" text-anchor="middle" class="clbl" font-size="12">PPS taps ×2</text>
<text x="305" y="578" text-anchor="middle" class="sub">UWB · scope</text>
<path class="net" d="M305,523 V545"/>
<text x="312" y="538" class="nettxt">fan-out</text>
<!-- NMEA UART note from GPS to 40-pin -->
<path class="net" d="M190,505 H410 V540" stroke-dasharray="4 3"/>
<text x="250" y="500" class="nettxt">NMEA→GPIO UART</text>
<rect x="40" y="650" width="18" height="12" class="pwr"/>
<text x="66" y="660" class="sub">power</text>
<rect x="140" y="650" width="18" height="12" class="cm5"/>
<text x="166" y="660" class="sub">module</text>
<rect x="250" y="650" width="18" height="12" class="conn"/>
<text x="276" y="660" class="sub">connector / peripheral</text>
<text x="960" y="700" text-anchor="end" class="sub">4-layer · controlled-Z (PCIe + GbE) · derive from CM5IO KiCad</text>
</svg>
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<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 920 660" font-family="'DejaVu Sans Mono', monospace">
<defs>
<style>
.board { fill:#0c3b2e; stroke:#1f6b53; stroke-width:2; }
.edgetxt { fill:#7fcbb4; }
.topconn { fill:#16324a; stroke:#4aa3d6; stroke-width:1.6; }
.toptxt { fill:#cfe8f7; font-size:12px; }
.topsub { fill:#7fa6c0; font-size:9.5px; }
.botconn { fill:none; stroke:#c98b3c; stroke-width:1.4; stroke-dasharray:5 3; }
.bottxt { fill:#e3b878; font-size:11px; }
.botsub { fill:#b08850; font-size:9px; }
.cm5 { fill:none; stroke:#d96f6f; stroke-width:2; stroke-dasharray:7 4; }
.cm5txt { fill:#e89a9a; font-size:13px; font-weight:bold; }
.hole { fill:#0a181d; stroke:#9fb4bb; stroke-width:1.5; }
.dim { fill:#8aa0a8; font-size:11px; }
.dimline { stroke:#5a7077; stroke-width:1; }
.title { fill:#eaf6f7; font-size:18px; font-weight:bold; }
.ttag { fill:#4aa3d6; font-size:10px; letter-spacing:2px; }
.leg { font-size:10px; }
</style>
</defs>
<rect x="0" y="0" width="920" height="660" fill="#08161b"/>
<text x="40" y="34" class="ttag">MECHANICAL PLACEMENT — TOP VIEW (not to exact scale, no routing)</text>
<text x="40" y="58" class="title">CM5 Carrier · ~85 × 56 mm · CM5 on bottom (X1507-style)</text>
<!-- Board outline: scale 8 px/mm -> 85mm=680, 56mm=448. Origin x=120 y=110 -->
<rect class="board" x="120" y="110" width="680" height="448" rx="14"/>
<!-- mounting holes (Pi HAT 58x49 pattern, M2.5) corners inset -->
<circle class="hole" cx="150" cy="140" r="7"/>
<circle class="hole" cx="770" cy="140" r="7"/>
<circle class="hole" cx="150" cy="528" r="7"/>
<circle class="hole" cx="770" cy="528" r="7"/>
<!-- ===== CM5 module footprint (bottom side, dashed) ===== -->
<!-- CM5 55x40mm => 440x320 px, centered-ish left -->
<rect class="cm5" x="250" y="190" width="320" height="288"/>
<text x="410" y="330" text-anchor="middle" class="cm5txt">CM5 (bottom)</text>
<text x="410" y="350" text-anchor="middle" class="cm5txt" font-size="10">55 × 40 mm</text>
<!-- the two DF40 connector strips (bottom) -->
<rect class="botconn" x="265" y="205" width="290" height="22"/>
<text x="410" y="220" text-anchor="middle" class="botsub">DF40 J1 (bottom)</text>
<rect class="botconn" x="265" y="441" width="290" height="22"/>
<text x="410" y="456" text-anchor="middle" class="botsub">DF40 J2MOD (bottom)</text>
<!-- ===== Bottom-side support chips (dashed amber) ===== -->
<rect class="botconn" x="585" y="190" width="120" height="34"/>
<text x="645" y="205" text-anchor="middle" class="botsub">15→5V buck 5A</text>
<text x="645" y="217" text-anchor="middle" class="botsub">(bottom)</text>
<rect class="botconn" x="585" y="232" width="120" height="34"/>
<text x="645" y="247" text-anchor="middle" class="botsub">15→3V3_RF 4A</text>
<text x="645" y="259" text-anchor="middle" class="botsub">(bottom)</text>
<rect class="botconn" x="585" y="274" width="120" height="30"/>
<text x="645" y="293" text-anchor="middle" class="botsub">15→3V3 AUX 1A</text>
<rect class="botconn" x="585" y="312" width="120" height="30"/>
<text x="645" y="331" text-anchor="middle" class="botsub">ideal-diode + TVS</text>
<rect class="botconn" x="585" y="350" width="120" height="30"/>
<text x="645" y="369" text-anchor="middle" class="botsub">Schmitt + xlat / ESD</text>
<!-- ===== TOP-SIDE connectors (along edges) ===== -->
<!-- Right edge I/O cluster: Ethernet, 2x USB-A, USB-C -->
<rect class="topconn" x="724" y="150" width="64" height="70" rx="3"/>
<text x="756" y="180" text-anchor="middle" class="toptxt">RJ45</text>
<text x="756" y="196" text-anchor="middle" class="topsub">GbE</text>
<rect class="topconn" x="724" y="232" width="64" height="46" rx="3"/>
<text x="756" y="252" text-anchor="middle" class="toptxt">USB-A</text>
<text x="756" y="266" text-anchor="middle" class="topsub">#1 USB3</text>
<rect class="topconn" x="724" y="290" width="64" height="46" rx="3"/>
<text x="756" y="310" text-anchor="middle" class="toptxt">USB-A</text>
<text x="756" y="324" text-anchor="middle" class="topsub">#2 USB3</text>
<rect class="topconn" x="724" y="348" width="64" height="40" rx="3"/>
<text x="756" y="366" text-anchor="middle" class="toptxt">USB-C</text>
<text x="756" y="380" text-anchor="middle" class="topsub">prog</text>
<!-- 15V inlet bottom-right edge -->
<rect class="topconn" x="700" y="500" width="88" height="44" rx="3"/>
<text x="744" y="520" text-anchor="middle" class="toptxt">15 VDC</text>
<text x="744" y="534" text-anchor="middle" class="topsub">jack / 2-pin</text>
<!-- M.2 E-key: top side, left-center -->
<rect class="topconn" x="150" y="300" width="150" height="40" rx="3"/>
<text x="225" y="320" text-anchor="middle" class="toptxt">M.2 E-key (2230)</text>
<text x="225" y="333" text-anchor="middle" class="topsub">Wi-Fi AW7915</text>
<circle class="hole" cx="290" cy="320" r="4"/>
<!-- 40-pin header: top edge -->
<rect class="topconn" x="150" y="128" width="430" height="30" rx="3"/>
<text x="365" y="148" text-anchor="middle" class="toptxt">40-pin GPIO header</text>
<!-- pin dots -->
<g fill="#4aa3d6">
<!-- decorative -->
</g>
<!-- 14-pin J2 + UART: bottom edge left -->
<rect class="topconn" x="150" y="508" width="180" height="30" rx="3"/>
<text x="240" y="528" text-anchor="middle" class="toptxt">14-pin (J2 ref)</text>
<rect class="topconn" x="344" y="508" width="90" height="30" rx="3"/>
<text x="389" y="528" text-anchor="middle" class="toptxt">UART</text>
<!-- GPS + PPS taps: left edge -->
<rect class="topconn" x="150" y="360" width="120" height="30" rx="3"/>
<text x="210" y="380" text-anchor="middle" class="toptxt">GPS (5-pin)</text>
<rect class="topconn" x="150" y="400" width="56" height="28" rx="3"/>
<text x="178" y="418" text-anchor="middle" class="topsub">PPS1</text>
<rect class="topconn" x="214" y="400" width="56" height="28" rx="3"/>
<text x="242" y="418" text-anchor="middle" class="topsub">PPS2</text>
<!-- RTC battery: center-bottom -->
<circle class="topconn" cx="470" cy="490" r="26"/>
<text x="470" y="487" text-anchor="middle" class="topsub">CR2032</text>
<text x="470" y="499" text-anchor="middle" class="topsub">RTC</text>
<!-- ===== Dimension lines ===== -->
<line class="dimline" x1="120" y1="585" x2="800" y2="585"/>
<line class="dimline" x1="120" y1="578" x2="120" y2="592"/>
<line class="dimline" x1="800" y1="578" x2="800" y2="592"/>
<text x="460" y="602" text-anchor="middle" class="dim">~85 mm</text>
<line class="dimline" x1="832" y1="110" x2="832" y2="558"/>
<line class="dimline" x1="825" y1="110" x2="839" y2="110"/>
<line class="dimline" x1="825" y1="558" x2="839" y2="558"/>
<text x="855" y="338" text-anchor="middle" class="dim" transform="rotate(90 855 338)">~56 mm</text>
<!-- ===== Legend ===== -->
<rect x="120" y="618" width="20" height="12" class="topconn"/>
<text x="148" y="628" class="leg" fill="#cfe8f7">top-side connector</text>
<rect x="300" y="618" width="20" height="12" fill="none" stroke="#c98b3c" stroke-width="1.4" stroke-dasharray="5 3"/>
<text x="328" y="628" class="leg" fill="#e3b878">bottom-side chip (dashed)</text>
<rect x="530" y="618" width="20" height="12" fill="none" stroke="#d96f6f" stroke-width="2" stroke-dasharray="7 4"/>
<text x="558" y="628" class="leg" fill="#e89a9a">CM5 module (bottom)</text>
<circle cx="740" cy="624" r="6" class="hole"/>
<text x="754" y="628" class="leg" fill="#9fb4bb">M2.5 mount</text>
</svg>
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 1,
"dimension_units": 2,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 2.7,
"height": 2.7,
"width": 2.7
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.39
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [
"clearance|139230000|150500000|44050c2e-137a-4ee5-aab6-af6e82cb550c|c1309054-b3ec-4f1e-9334-00cba6baa146",
"clearance|140500000|149230000|fcebfa8a-eb3d-4196-9404-532dc9ddde9f|c1309054-b3ec-4f1e-9334-00cba6baa146",
"clearance|140920000|151770000|40ece557-24f2-47a4-bf57-058580957d62|44050c2e-137a-4ee5-aab6-af6e82cb550c",
"clearance|141770000|150920000|40ece557-24f2-47a4-bf57-058580957d62|fcebfa8a-eb3d-4196-9404-532dc9ddde9f",
"clearance|146205000|147060000|cf9a04ac-e742-4cc4-b820-74b94e875632|fd267553-ab4f-45b2-b9de-3fd8c755208d",
"clearance|159795000|147060000|386d8066-f8d7-448e-8535-fb964d94eab0|49b00fb2-fbf7-4862-ac04-916c407cd0f2",
"clearance|159975000|145410000|029ebbb9-b02f-45bd-96ed-01f4d0ed11f9|8cfd9587-a6c9-4a80-b337-75a1568e78eb",
"clearance|163003858|146776424|a2c51ef8-4a45-4b19-8a83-e2fa4ed59648|49b00fb2-fbf7-4862-ac04-916c407cd0f2",
"courtyards_overlap|124749999|104420001|00000000-0000-0000-0000-00005d2e9306|00000000-0000-0000-0000-00005e42b6ed",
"footprint_type_mismatch|187000000|157525000|00000000-0000-0000-0000-00005d2fec1a|00000000-0000-0000-0000-000000000000"
],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "warning",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "warning",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "warning",
"padstack": "error",
"pth_inside_courtyard": "warning",
"shorting_items": "error",
"silk_edge_clearance": "ignore",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "ignore",
"starved_thermal": "ignore",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.125,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_clearance": 0.19,
"min_hole_to_hole": 0.24,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.2,
"min_track_width": 0.1,
"min_via_annular_width": 0.1,
"min_via_annulus": 0.049999999999999996,
"min_via_diameter": 0.45,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.127,
0.13,
0.147,
0.2,
0.23,
0.3,
0.5,
1.0,
2.0,
3.0
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 100,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 100,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 100,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.45,
"drill": 0.2
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [
"power_pin_not_driven|1003300|1181100|66cf9899-100d-45fb-9b9f-8f866de8a3fe|00000000-0000-0000-0000-000000000000|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|",
"power_pin_not_driven|1524000|317500|2cecda96-8fc5-40d2-a9f4-ae1444adbd06|00000000-0000-0000-0000-000000000000|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005ed4bb5b|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005ed4bb5b|",
"power_pin_not_driven|393700|1181100|0fc4267c-2119-444e-b3b2-d8a7bd88ec8a|00000000-0000-0000-0000-000000000000|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|"
],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "error",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "error",
"net_not_bus_member": "error",
"no_connect_connected": "error",
"no_connect_dangling": "error",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "error",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "CM5IO.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.125,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.13,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.13,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.13,
"diff_pair_gap": 0.253,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.127,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "100R",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.13,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.178,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "50R",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.13,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.13,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.13,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "75R",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.13,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.13,
"diff_pair_gap": 0.253,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.147,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "90R",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.147,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.13,
"diff_pair_gap": 0.253,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.127,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "HDMI",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 1.0,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.13,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "POE TAPS",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "90R",
"pattern": "/CM5_HighSpeed/USB3*"
},
{
"netclass": "100R",
"pattern": "/CM5_HighSpeed/DPHY*"
},
{
"netclass": "HDMI",
"pattern": "/CM5_HighSpeed/HDMI*_D*"
},
{
"netclass": "HDMI",
"pattern": "/CM5_HighSpeed/HDMI*_CK*"
},
{
"netclass": "POE TAPS",
"pattern": "/CM5_GPIO ( Ethernet, GPIO, SDCARD)/TR*_TAP"
},
{
"netclass": "100R",
"pattern": "/CM5_GPIO ( Ethernet, GPIO, SDCARD)/TRD*"
},
{
"netclass": "90R",
"pattern": "/CM5_HighSpeed/PCIE_*X_*"
},
{
"netclass": "90R",
"pattern": "/CM5_HighSpeed/PCIE_*CLK_*"
},
{
"netclass": "90R",
"pattern": "/USB2*"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "CM5IOUSB3.cad",
"idf": "",
"netlist": "CM5IO.net",
"plot": "./",
"pos_files": "RPI-CM5IO-Gerber200924/",
"specctra_dsn": "",
"step": "",
"svg": "SVG/",
"vmrl": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": true,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": false,
"label": "#",
"name": "${ITEM_NUMBER}",
"show": false
},
{
"group_by": false,
"label": "Field4",
"name": "Field4",
"show": true
},
{
"group_by": false,
"label": "Field5",
"name": "Field5",
"show": true
},
{
"group_by": false,
"label": "Field6",
"name": "Field6",
"show": true
},
{
"group_by": false,
"label": "Field7",
"name": "Field7",
"show": true
},
{
"group_by": false,
"label": "Field8",
"name": "Field8",
"show": true
},
{
"group_by": false,
"label": "Part Description",
"name": "Part Description",
"show": true
},
{
"group_by": false,
"label": "Description",
"name": "Description",
"show": false
}
],
"filter_string": "",
"group_symbols": true,
"name": "",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.3,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "./SVG",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"e63e39d7-6ac0-4ffd-8aa3-1841a4541b55",
"Root"
],
[
"00000000-0000-0000-0000-00005cff70b1",
"CM5_HighSpeed"
],
[
"00000000-0000-0000-0000-00005cff706a",
"CM5_GPIO ( Ethernet, GPIO, SDCARD)"
],
[
"00000000-0000-0000-0000-00005ed4bb5b",
"PCIe-M2"
]
],
"text_variables": {}
}

3936
refs/CM5IO.kicad_sch Normal file
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10220
refs/CM5IO.kicad_sym Normal file
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607
refs/CM5IO.pretty/BatteryHolder_Keystone_3034_1x20mm.kicad_mod Normal file
View File

@@ -0,0 +1,607 @@
(footprint "BatteryHolder_Keystone_3034_1x20mm"
(version 20240108)
(generator "pcbnew")
(generator_version "8.0")
(layer "F.Cu")
(descr "Keystone 3034 SMD battery holder for 2020, 2025 and 2032 coincell batteries. http://www.keyelco.com/product-pdf.cfm?p=798")
(tags "Keystone type 3034 coin cell retainer")
(property "Reference" "BT1"
(at -10.4 -8.7 -90)
(layer "F.SilkS")
(uuid "ebefe269-e788-4831-abcf-162d5b2e19d8")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Value" "Battery_Cell"
(at 0 11.5 180)
(layer "F.Fab")
(uuid "b42adde4-6221-4f46-b2b7-09c308b87d14")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Footprint" "BatteryHolder_Keystone_3034_1x20mm"
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "7a61d7ab-97ad-40c2-8d78-a27f026c6c43")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Datasheet" "https://www.keyelco.com/userAssets/file/M65p9.pdf"
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "a9139876-9066-4d18-b6bf-cb1f6e670b81")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Description" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "1ad871f1-45c6-4ebb-b5c4-294c2ec3fac7")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Field4" "Digikey"
(at 0 0 -90)
(layer "F.Fab")
(hide yes)
(uuid "8a69b0bb-7ee2-42c3-b5fa-59b6616b692f")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Field5" "36-3034-ND"
(at 0 0 -90)
(layer "F.Fab")
(hide yes)
(uuid "7704aa70-1cd1-4e58-9ff6-cb6a0b6e6914")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Field6" "3034"
(at 0 0 -90)
(layer "F.Fab")
(hide yes)
(uuid "c6b7bd9e-aaa0-4cad-b9f4-a86442160478")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Field7" "Keystone"
(at 0 0 -90)
(layer "F.Fab")
(hide yes)
(uuid "5900fec3-a084-4b1c-ab31-468b558bfb72")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Part Description" " Battery Retainer Coin, 20.0mm 1 Cell SMD (SMT) Tab"
(at 0 0 -90)
(layer "F.Fab")
(hide yes)
(uuid "c3defbff-873d-432b-bbdf-e359dc2e376d")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(attr smd)
(fp_line
(start -10.78 -5.46)
(end -10.78 -3)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "b43e530c-70bd-45d6-83d7-cab6a3120bca")
)
(fp_line
(start -10.78 3)
(end -10.78 3.63)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "73f0b823-ca49-46c0-8160-1044c3676fd4")
)
(fp_line
(start -10.78 3.63)
(end -9.34 7.58)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "2b98f197-cc89-4919-8eaa-3c5628f531bc")
)
(fp_line
(start -8.7 -7.54)
(end -10.78 -5.46)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "9a7dd8fe-d376-4c6e-97cf-eb42292afaaa")
)
(fp_line
(start -5.2 -7.54)
(end -8.7 -7.54)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "85ddb1f0-e97c-405c-9f70-ea36a36ff1e2")
)
(fp_line
(start 8.7 -7.54)
(end 5.2 -7.54)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "711e0cff-9778-46e0-9a00-6fbe78e08da1")
)
(fp_line
(start 8.7 -7.54)
(end 10.78 -5.46)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "353afd48-967f-41ab-aa39-1e822bdb1fe4")
)
(fp_line
(start 10.78 -5.46)
(end 10.78 -3)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "b56a2ece-371d-44e6-ac97-d8b5b2cfe9be")
)
(fp_line
(start 10.78 3)
(end 10.78 3.63)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "3ae75835-766d-4979-9a66-bed02b7afa33")
)
(fp_line
(start 10.78 3.63)
(end 9.34 7.58)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "94df33d8-0342-47e4-9d6d-52b10025d8f2")
)
(fp_arc
(start -6.003354 8.56653)
(mid -7.921654 8.918738)
(end -9.34 7.58)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "f60b4707-270d-4846-8a0a-5a0c64b9ec52")
)
(fp_arc
(start 9.325243 7.588169)
(mid 7.90634 8.911668)
(end 6 8.55)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "d123fe73-cdd8-4c6d-8808-ecc654322a99")
)
(fp_circle
(center 0 0)
(end 0 10.25)
(stroke
(width 0.15)
(type solid)
)
(fill none)
(layer "Dwgs.User")
(uuid "670dffa6-14da-4efe-9e8e-fa8efea3e936")
)
(fp_line
(start -12.37 -2.79)
(end -12.37 2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "9469d6c6-41da-4797-80e2-1ee26b2e9947")
)
(fp_line
(start -12.37 2.79)
(end -10.88 2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "84e480b7-2009-4e7b-9684-6e216cc40550")
)
(fp_line
(start -10.88 -5.5)
(end -10.88 -2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "20e6cf31-f568-47ab-a9ed-0d9af19187d2")
)
(fp_line
(start -10.88 -2.79)
(end -12.37 -2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "9fbfeb2a-36e6-4575-9cc2-05d684ea53d7")
)
(fp_line
(start -10.88 2.79)
(end -10.88 3.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "99ef1d1a-fb62-4425-b0c7-29b27c9c6805")
)
(fp_line
(start -10.88 3.64)
(end -9.44 7.62)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "e761258d-aa2a-4b8f-94bd-cda354ba4dea")
)
(fp_line
(start -8.74 -7.64)
(end -10.88 -5.5)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "4d14f4a6-9703-4595-a5a1-9f9f7d878938")
)
(fp_line
(start -7.2 -7.64)
(end -8.74 -7.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "fe24e45b-47da-42b2-9323-b0eccd3ac77e")
)
(fp_line
(start 8.74 -7.64)
(end 7.2 -7.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "9decbbc4-3a0e-4130-8c8d-c5c51487e064")
)
(fp_line
(start 9.43 7.63)
(end 10.88 3.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "441a0a56-c5c7-4ec4-b81e-54f00c9cb216")
)
(fp_line
(start 10.88 -5.5)
(end 8.74 -7.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "3bb9d6ec-cc11-486b-bdc3-9edf8d52fb5f")
)
(fp_line
(start 10.88 -2.79)
(end 10.88 -5.5)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "6c0c97c7-761d-4897-b372-3b19d75279bf")
)
(fp_line
(start 10.88 2.79)
(end 12.37 2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "b41d9474-2033-40bc-82b8-3e10822a3645")
)
(fp_line
(start 10.88 3.64)
(end 10.88 2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "a9cdcb4a-0801-4642-9e67-d8578123139b")
)
(fp_line
(start 12.37 -2.79)
(end 10.88 -2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "ad1957ab-0a92-4cb6-870d-08a70ba446bb")
)
(fp_line
(start 12.37 2.79)
(end 12.37 -2.79)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "63324c9b-10cc-4631-a3a1-5ca3c997fddf")
)
(fp_arc
(start -7.199546 -7.640427)
(mid 0.000312 -10.498075)
(end 7.2 -7.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "8a67a9b9-bb4c-4a07-ac91-8b7070093fdf")
)
(fp_arc
(start -5.956965 8.654604)
(mid -7.953941 9.011629)
(end -9.43 7.62)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "effda7e0-34aa-4e10-ab78-1f8c3428e5ef")
)
(fp_arc
(start 5.945368 8.650075)
(mid -0.008883 10.496243)
(end -5.96 8.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "4fc02490-5fcc-43b3-a1d2-14f36f0b2b52")
)
(fp_arc
(start 9.415144 7.621341)
(mid 7.944017 9.000493)
(end 5.96 8.64)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "704d3af3-696f-48e5-9ac8-e6c31e522b98")
)
(fp_line
(start -10.63 -5.4)
(end -8.64 -7.39)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "ee451a69-4fd1-4a06-815b-74a365c75965")
)
(fp_line
(start -10.63 3.6)
(end -10.63 -5.4)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "30badde5-cfa3-4bab-b9dd-647b0b53b15e")
)
(fp_line
(start -9.19 7.53)
(end -10.63 3.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "038c7cfb-b761-407b-b83c-228f5db735ed")
)
(fp_line
(start -8.64 -7.39)
(end 8.64 -7.39)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "d471b3bb-07c5-49e6-ab3e-dc7cd2e4be62")
)
(fp_line
(start 8.64 -7.39)
(end 10.63 -5.4)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "01684eba-a26b-454c-8518-ad2f2fbfd34f")
)
(fp_line
(start 10.63 -5.4)
(end 10.63 3.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "6a8d73cc-71f8-4238-96bc-e816a111111e")
)
(fp_line
(start 10.63 3.6)
(end 9.19 7.53)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "9ef22064-0bb0-434c-bb80-76a04081efe8")
)
(fp_arc
(start -6.096146 8.438508)
(mid -7.87328 8.768206)
(end -9.19 7.53)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "13282a34-b409-4098-8417-dc5d41f5bf4b")
)
(fp_arc
(start -6.094852 8.426043)
(mid 0.003247 6.355257)
(end 6.1 8.43)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "f11acc92-2fec-429a-9e6d-610b7306f061")
)
(fp_arc
(start 9.180727 7.528882)
(mid 7.868698 8.760067)
(end 6.1 8.43)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "2ff949ba-139e-4ea0-8ee6-6673d9db4f50")
)
(fp_text user "${REFERENCE}"
(at 0 -2.9 180)
(layer "F.Fab")
(uuid "100c134e-792b-40f5-90c7-aa76dd570637")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(pad "1" smd rect
(at -11.485 0)
(size 1.77 5.08)
(layers "F.Cu" "F.Paste" "F.Mask")
(uuid "77289ecf-1789-4799-bbb7-9dae540091ce")
)
(pad "1" smd rect
(at 11.485 0)
(size 1.77 5.08)
(layers "F.Cu" "F.Paste" "F.Mask")
(uuid "ed34a86a-3b47-4fc6-86d1-18e6407d8c39")
)
(pad "2" smd circle
(at 0 0)
(size 17.8 17.8)
(layers "F.Cu" "F.Mask")
(uuid "649be996-f766-451e-b3a7-36ec4840ceee")
)
(model "${KICAD8_3DMODEL_DIR}/Battery.3dshapes/BatteryHolder_Keystone_3034_1x20mm.wrl"
(offset
(xyz 0 0 0)
)
(scale
(xyz 1 1 1)
)
(rotate
(xyz 0 0 0)
)
)
)

80
refs/CM5IO.pretty/EDAC 690-019-298-412.kicad_mod Normal file
View File

@@ -0,0 +1,80 @@
(footprint "EDAC 690-019-298-412" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(attr through_hole)
(fp_text reference "EDAC 690-019-298-412" (at 0 11.2) (layer "F.SilkS")
(effects (font (size 0.800457 0.800457) (thickness 0.05)))
(tstamp 7caa8234-36bb-45fc-af43-47be604f31bb)
)
(fp_text value "VAL**" (at -6.1 -2.9) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 39eec2e1-2743-4b9b-afe2-7d18ba670474)
)
(fp_line (start -8.1 4.7) (end -8.1 1.8)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 5017c7f1-95a0-4b40-84f7-7fa9921a2552))
(fp_line (start -8.1 9.55) (end -8.1 7.2)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp c7dc6535-ddb4-41be-b128-e46e3b6caf3e))
(fp_line (start -8.1 9.55) (end 8.1 9.55)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 5e2606a3-9406-4d00-9b52-51202c789d6c))
(fp_line (start -6.7 -2) (end -5.2 -2)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp f788d226-12ad-4007-afee-08258297ca4f))
(fp_line (start 5.6 -2) (end 6.7 -2)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 38265fcd-2456-4ccc-8d4c-fe52ca2ba093))
(fp_line (start 8.1 1.9) (end 8.1 4.7)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp f8849aea-80e4-4f07-9028-3bd9b956b7f0))
(fp_line (start 8.1 7.1) (end 8.1 9.55)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 113b8ad8-205f-4aca-ae1f-8e240583e7a4))
(fp_circle (center 5.3 -2.5) (end 5.4 -2.5)
(stroke (width 0.2) (type solid)) (fill none) (layer "F.SilkS") (tstamp 05cc1c77-e54e-40ec-ad9b-ab56870ef27d))
(fp_line (start -8.35 -2.2) (end 8.4 -2.2)
(stroke (width 0.05) (type solid)) (layer "Eco1.User") (tstamp 691d196e-0499-4575-8ed1-0d44aa5fe3bf))
(fp_line (start -8.35 8.5) (end -8.35 -2.2)
(stroke (width 0.05) (type solid)) (layer "Eco1.User") (tstamp 0ab531ac-e7ca-4be5-82e7-b8c6dbc6e799))
(fp_line (start -8.35 9.5) (end -8.35 8.5)
(stroke (width 0.05) (type solid)) (layer "Eco1.User") (tstamp 4535f2cb-8fa8-4860-a1c7-57eb4d8d2e47))
(fp_line (start 8.4 -2.2) (end 8.4 9.5)
(stroke (width 0.05) (type solid)) (layer "Eco1.User") (tstamp 605dc4bc-8ad1-431d-9063-317cb76647f5))
(fp_line (start 8.4 9.5) (end -8.35 9.5)
(stroke (width 0.05) (type solid)) (layer "Eco1.User") (tstamp 183d60e1-c382-4fae-9685-0c5cb5c5c7b8))
(fp_line (start -8.1 -2) (end 8.1 -2)
(stroke (width 0.127) (type solid)) (layer "Eco2.User") (tstamp 67227786-b67f-4a4a-b05d-2e2b5fd44a4e))
(fp_line (start -8.1 8.5) (end -8.1 -2)
(stroke (width 0.127) (type solid)) (layer "Eco2.User") (tstamp 174abe2e-d37c-4b91-b0db-87f062cccc95))
(fp_line (start -8.1 10.55) (end -8.1 8.5)
(stroke (width 0.127) (type solid)) (layer "Eco2.User") (tstamp 4475b990-be3f-4481-aacc-9fb34fe78b07))
(fp_line (start 8.1 -2) (end 8.1 8.5)
(stroke (width 0.127) (type solid)) (layer "Eco2.User") (tstamp 2ca35f9a-6903-4102-bee3-cdacdc748f0a))
(fp_line (start 8.1 8.5) (end 8.1 10.55)
(stroke (width 0.127) (type solid)) (layer "Eco2.User") (tstamp 4e6678f4-a838-4be5-9c8b-c5c145ada8b7))
(fp_line (start 8.1 10.55) (end -8.1 10.55)
(stroke (width 0.127) (type solid)) (layer "Eco2.User") (tstamp 07879fc0-0639-4805-992a-fb2578292e48))
(fp_rect (start -8.4 -2.3) (end 8.5 9.6)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd") (tstamp a2115308-c205-450e-9632-c0a17c820892))
(pad "1" smd rect (at 4.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fb3ecc2e-ade2-4f60-87bb-cb1e9fcbf558))
(pad "2" smd rect (at 4 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9d4448fa-a871-4b1d-812f-1c70ff166c74))
(pad "3" smd rect (at 3.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f25a2bb8-2f0a-4976-9f2c-0cf349c0dbeb))
(pad "4" smd rect (at 3 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fb25339e-e1d2-4cd7-9f39-be315f110559))
(pad "5" smd rect (at 2.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c9969d9a-72c3-4fe3-a15e-d44670d0acb0))
(pad "6" smd rect (at 2 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3ec89edf-f9f0-4b92-b789-db72cc0d09c2))
(pad "7" smd rect (at 1.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9abddd0d-fafb-4910-8c0f-e54f82d714c9))
(pad "8" smd rect (at 1 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 287371a8-55af-41ed-8eea-5e1e402a2908))
(pad "9" smd rect (at 0.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 0a7906ff-a4db-4afb-b5fa-cf70c50a84d4))
(pad "10" smd rect (at 0 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp af3ae067-b88d-4668-97bc-18eec07999b5))
(pad "11" smd rect (at -0.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b502eef7-f382-4046-852b-3d9483524141))
(pad "12" smd rect (at -1 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c3134f3e-1eb4-4ede-864c-5c17a40f3fd3))
(pad "13" smd rect (at -1.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 60b967c8-126e-4bb0-a98d-cd9c5eed8014))
(pad "14" smd rect (at -2 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b590a9a6-107d-4b6c-bf70-1a6c82b46a3a))
(pad "15" smd rect (at -2.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 12045232-5314-4c03-914a-1cafeca86a20))
(pad "16" smd rect (at -3 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ad84a92c-93e2-4beb-9f21-d9744aaaf8b9))
(pad "17" smd rect (at -3.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 38c34b77-a067-4560-959f-86583f83312f))
(pad "18" smd rect (at -4 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e297dfbb-c6e7-4d5c-8479-804133132fad))
(pad "19" smd rect (at -4.5 -0.73 90) (size 2.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1c3325b0-97e4-4dfe-9010-7836799cd80a))
(pad "SH1" thru_hole oval (at 7.25 0) (size 1.5 3.3) (drill oval 0.9 2.7) (layers "*.Cu" "*.Mask") (tstamp e3205586-cda5-4187-9187-80794490bd82))
(pad "SH2" thru_hole oval (at -7.25 0) (size 1.5 3.3) (drill oval 0.9 2.7) (layers "*.Cu" "*.Mask") (tstamp 326886f7-b68e-4ee7-b9bd-075080b943b1))
(pad "SH3" thru_hole oval (at -7.25 5.96) (size 1.5 2.3) (drill oval 0.9 1.7) (layers "*.Cu" "*.Mask") (tstamp 4f4b37e0-4680-433b-bd8b-2ad65c9275c8))
(pad "SH4" thru_hole oval (at 7.25 5.96) (size 1.5 2.3) (drill oval 0.9 1.7) (layers "*.Cu" "*.Mask") (tstamp 59b63a7a-6614-4c15-8006-94f07b2db07f))
(model "${KIPRJMOD}/CM5IO.3dshapes/471511051.stp"
(offset (xyz 0 -10.5 3.5))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)

105
refs/CM5IO.pretty/Hirose_FH12-22S-0.5SH_1x22-1MP_P0.50mm_Horizontal.kicad_mod Normal file
View File

@@ -0,0 +1,105 @@
(footprint "Hirose_FH12-22S-0.5SH_1x22-1MP_P0.50mm_Horizontal" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "Molex FH12, FFC/FPC connector, FH12-22S-0.5SH, 22 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator")
(tags "connector Hirose top entry")
(attr smd)
(fp_text reference "HirsoeFH12-22S-05SH_1x22-1MP4" (at 0 -3.7 180) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 6c2b8449-6d0f-4cd5-9ed8-ab76d81fb238)
)
(fp_text value "Conn_01x22_Female" (at 0 5.6 180) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 62e0e569-8677-4f77-84bb-eb3a49cae1a5)
)
(fp_text user "${REFERENCE}" (at 0 3.7 180) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp e16affbe-e639-4134-90c1-2a26dee98d83)
)
(fp_line (start -7.15 -1.3) (end -7.15 0.04)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ea5a2062-f746-4619-97f4-0774fc4b13fb))
(fp_line (start -7.15 2.76) (end -7.15 4.5)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 366939ff-f9e9-4215-aca5-bc1225afb29f))
(fp_line (start -7.15 4.5) (end 7.15 4.5)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp cb96798b-c348-4c00-ba09-4c9fa1ef72ce))
(fp_line (start -5.66 -1.3) (end -7.15 -1.3)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ddfc433c-047d-442f-9166-92787492c54a))
(fp_line (start -5.66 -1.3) (end -5.66 -2.5)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 48e1197c-d3e4-4b47-856d-cd18944a4f08))
(fp_line (start 5.66 -1.3) (end 7.15 -1.3)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8318cdbe-04d5-4eea-be41-7db3393ce812))
(fp_line (start 7.15 -1.3) (end 7.15 0.04)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f9420751-2b9b-4951-8aee-61469c1fced3))
(fp_line (start 7.15 4.5) (end 7.15 2.76)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 598a4809-e866-47d3-a5a8-8f05d1276e8b))
(fp_circle (center 6.28 -1.94) (end 6.61 -1.69)
(stroke (width 0.12) (type solid)) (fill none) (layer "F.SilkS") (tstamp a1f139ce-7a97-41ff-9e77-90f9baf4d752))
(fp_line (start -8.55 -3) (end -8.55 4.9)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f878114a-ed93-4d11-b160-9b89a2068be4))
(fp_line (start -8.55 4.9) (end 8.55 4.9)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 968b1b76-3fd9-43e1-a821-14f8878b822f))
(fp_line (start 8.55 -3) (end -8.55 -3)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 2588b7db-04b7-4d59-9fb6-0731fae3086b))
(fp_line (start 8.55 4.9) (end 8.55 -3)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a82d6525-c95b-456e-a4ad-89ebd7e51e65))
(fp_line (start -7.05 -1.2) (end -7.05 3.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 27a4cb8a-f923-4488-9796-42b64d86aa97))
(fp_line (start -7.05 3.4) (end -6.45 3.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp abd29752-4ec4-484d-a025-86883e9834f2))
(fp_line (start -6.95 3.7) (end -6.95 4.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d71232b4-3f3b-4d3c-a68c-0695ef0e6b70))
(fp_line (start -6.95 4.4) (end 0 4.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4a9a5637-3610-4832-aff0-682bf1924d33))
(fp_line (start -6.45 3.4) (end -6.45 3.7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp f371a564-9c0f-40b0-8ca2-4c6958e0a701))
(fp_line (start -6.45 3.7) (end -6.95 3.7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d24794fc-4f23-414e-8ead-b5741c2d711c))
(fp_line (start 0 -1.2) (end -7.05 -1.2)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp efec4023-7ed0-4f88-afae-8a87032fc06d))
(fp_line (start 0 -1.2) (end 7.05 -1.2)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 90abf610-d26b-4a39-b1f5-9594c1892d16))
(fp_line (start 6.29 -1.91) (end 5.79 -1.202893)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp f82a6bff-b2a9-4d1d-a546-b0bdc7554b10))
(fp_line (start 6.45 3.4) (end 6.45 3.7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a267c7f0-a2ae-4931-93b7-11a51ffc5267))
(fp_line (start 6.45 3.7) (end 6.95 3.7)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 2898c334-e3e2-4ab7-a3e5-600044d3a13c))
(fp_line (start 6.79 -1.202893) (end 6.29 -1.91)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 342fa5d9-de9b-45e9-ae8f-d0d0fe7cc322))
(fp_line (start 6.95 3.7) (end 6.95 4.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 3eb43dd5-d5ab-456c-9ed9-cf44830b3a8f))
(fp_line (start 6.95 4.4) (end 0 4.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 8700ccd5-1535-4038-bac7-a1cc0d501198))
(fp_line (start 7.05 -1.2) (end 7.05 3.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 74f27d3d-e0b2-4868-b895-95e8a42e3461))
(fp_line (start 7.05 3.4) (end 6.45 3.4)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 6cbfca48-63ee-4a83-819f-0d03202d4453))
(pad "1" smd rect (at 5.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp af63cb8c-c1b1-44e4-8d15-4c3b706f67be))
(pad "2" smd rect (at 4.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5615e8a3-e4f8-43dd-bcbc-6625993e2b64))
(pad "3" smd rect (at 4.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d34aee20-c735-4345-afdf-fd3c31720cce))
(pad "4" smd rect (at 3.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1a2bde7d-ae14-42eb-8cbe-c2740b289c01))
(pad "5" smd rect (at 3.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3f5fd77d-fdd3-4f8b-b966-95fcc906d806))
(pad "6" smd rect (at 2.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 893ed581-cbe2-4dc7-8076-6e9a06419c93))
(pad "7" smd rect (at 2.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 47de07fa-1ff6-4780-8a30-294dde7afc09))
(pad "8" smd rect (at 1.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 8a0b7216-a159-431c-b9e6-5ca37b2dd6e2))
(pad "9" smd rect (at 1.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e8b536b8-12c2-4f31-9d50-88a94fcf797d))
(pad "10" smd rect (at 0.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c9adba1-0823-4f69-a928-9cfdc7105865))
(pad "11" smd rect (at 0.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6a86dc6-3f6f-4b41-9b67-af75df97a39e))
(pad "12" smd rect (at -0.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6c5e1fd9-c3c4-4e14-8752-1653cb57488c))
(pad "13" smd rect (at -0.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 00ef44a2-ff92-4343-8c96-9f064f05d0b4))
(pad "14" smd rect (at -1.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b0a29ba4-e4f1-4a49-a0ac-f00b66a71a91))
(pad "15" smd rect (at -1.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6bfa466-4035-49d2-9e32-298127d990af))
(pad "16" smd rect (at -2.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 0e8595c9-a8d8-4382-a9c8-9a1971ed3b37))
(pad "17" smd rect (at -2.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5b9dee4e-5b9d-461c-923e-fe92f92f8308))
(pad "18" smd rect (at -3.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 94aa23c7-b0d3-40d6-82d5-1c8a0e756841))
(pad "19" smd rect (at -3.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6c2ce6e-e033-4ce9-9056-0a5c8b5d84a9))
(pad "20" smd rect (at -4.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3cbf55e9-bc52-4ba5-8fbf-046b325e2791))
(pad "21" smd rect (at -4.75 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3ebef04d-3a39-42b8-b8bd-9c38d10000cd))
(pad "22" smd rect (at -5.25 -1.85) (size 0.3 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f9eefa8f-1e5a-4ca5-9d9c-01150f569d57))
(pad "MP" smd rect (at -7.15 1.4) (size 1.8 2.2) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6d9e35d5-792c-42bc-9824-d2b9fad42806))
(pad "MP" smd rect (at 7.15 1.4) (size 1.8 2.2) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 106de9ea-aa6f-45a1-b412-2f07ca97222a))
(model "${KIPRJMOD}/CM5IO.3dshapes/FH12-22S-0.5SH.stp"
(offset (xyz 16.5 -10.6 -128))
(scale (xyz 1 1 1))
(rotate (xyz 0 90 180))
)
)

353
refs/CM5IO.pretty/L_Bourns_SRP5030CC.kicad_mod Normal file
View File

@@ -0,0 +1,353 @@
(footprint "L_Bourns_SRP5030CC"
(version 20240108)
(generator "pcbnew")
(generator_version "8.0")
(layer "F.Cu")
(descr "Inductor, Bourns, SRP5030T, 5.7mmx5.2mm (Script generated with StandardBox.py) (https://www.bourns.com/data/global/pdfs/SRP5030T.pdf)")
(tags "Inductor Bourns_SRP5030T")
(property "Reference" "REF**"
(at -0.35 -3.8 0)
(layer "F.SilkS")
(uuid "4ecbffd5-0873-4f3b-9b82-31bfb3b2b55d")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Value" "L_Bourns_SRP5030CC"
(at 0 3.6 0)
(layer "F.Fab")
(uuid "d82e602b-4b0f-41b1-8d1f-d278ff2a27c1")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Footprint" "L_Bourns_SRP5030CC"
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "386c9fa6-e9ce-4968-89d8-5e9798dd8488")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Datasheet" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "b3f49393-dd40-49a2-a86c-a14310454c49")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Description" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "febffb4c-700d-48df-8051-2ff03cff9e0a")
(effects
(font
(size 1.27 1.27)
)
)
)
(attr smd)
(fp_line
(start -3.35 -3.1)
(end -1.62 -3.1)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "10e29e2e-2431-4f76-adfc-2d3fbc789677")
)
(fp_line
(start -3.35 -1.8)
(end -3.35 -3.1)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "8257503b-a356-467b-b9f9-6287584fa662")
)
(fp_line
(start -2.97 -2.72)
(end -2.97 -1.8)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "f46219fb-aa42-463d-a690-912bfab955ee")
)
(fp_line
(start -2.97 -2.72)
(end 2.97 -2.72)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "36b525e7-e3d9-4f2f-b427-57ef7b168373")
)
(fp_line
(start -2.97 1.8)
(end -2.97 2.72)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "f5150185-2666-4a79-a80c-d411f9b847e1")
)
(fp_line
(start -2.97 2.72)
(end 2.97 2.72)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "d61b2765-369f-48d4-935e-91b51efdb9f5")
)
(fp_line
(start 2.97 -2.72)
(end 2.97 -1.8)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "30a9fa2b-11c9-4465-ae55-6890fc1c8c45")
)
(fp_line
(start 2.97 1.8)
(end 2.97 2.72)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "2ea485d9-5366-494d-8159-5957e4c01cab")
)
(fp_line
(start -3.5 -1.8)
(end -3.1 -1.8)
(stroke
(width 0.05)
(type default)
)
(layer "F.CrtYd")
(uuid "63d489d9-cf15-456e-9ce6-0b8ff2dc54d4")
)
(fp_line
(start -3.5 1.8)
(end -3.5 -1.8)
(stroke
(width 0.05)
(type default)
)
(layer "F.CrtYd")
(uuid "96636774-b28a-43e7-a866-5379f7378a28")
)
(fp_line
(start -3.1 -2.85)
(end -3.1 -1.8)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "fed538a1-a08c-4839-84bd-9a9be0fd1d42")
)
(fp_line
(start -3.1 -2.85)
(end 3.1 -2.85)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "867a1ae9-c8c3-42fc-8c84-638308709ca1")
)
(fp_line
(start -3.1 1.8)
(end -3.5 1.8)
(stroke
(width 0.05)
(type default)
)
(layer "F.CrtYd")
(uuid "07d95f05-dc87-4a73-baf3-19954587f1b6")
)
(fp_line
(start -3.1 1.8)
(end -3.1 2.85)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "ba73262f-6b79-4cd6-b915-e1cde297da7c")
)
(fp_line
(start -3.1 2.85)
(end 3.1 2.85)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "3c81df8d-7d19-4be1-aa94-b8a8c7458b11")
)
(fp_line
(start 3.1 -2.85)
(end 3.1 -1.8)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "6e5a0017-3e2c-48c2-882f-dcd82eb3f44e")
)
(fp_line
(start 3.1 -1.8)
(end 3.5 -1.8)
(stroke
(width 0.05)
(type default)
)
(layer "F.CrtYd")
(uuid "0f04a28a-1f31-4c53-a30d-b223c6b7d619")
)
(fp_line
(start 3.1 1.8)
(end 3.1 2.85)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "3f5f2975-6824-4c4e-9f6f-cd2d71528b95")
)
(fp_line
(start 3.5 -1.8)
(end 3.5 1.8)
(stroke
(width 0.05)
(type default)
)
(layer "F.CrtYd")
(uuid "17e0300e-11fa-4619-afea-ddfc4751eddd")
)
(fp_line
(start 3.5 1.8)
(end 3.1 1.8)
(stroke
(width 0.05)
(type default)
)
(layer "F.CrtYd")
(uuid "7b4850c8-531a-47cd-911a-c5ba52ac7405")
)
(fp_line
(start -2.85 -1.6)
(end -1.85 -2.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "24194518-ead2-4ae5-afdd-48b8f1246eeb")
)
(fp_line
(start -2.85 2.6)
(end -2.85 -1.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "32464982-5230-48fc-8620-9755150f2375")
)
(fp_line
(start -1.85 -2.6)
(end 2.85 -2.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "c832142a-3e19-4a9e-b43b-a918e43f9864")
)
(fp_line
(start 2.85 -2.6)
(end 2.85 2.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "847a0556-aaba-43bf-8d5e-6b75aa225745")
)
(fp_line
(start 2.85 2.6)
(end -2.85 2.6)
(stroke
(width 0.1)
(type solid)
)
(layer "F.Fab")
(uuid "320a51c6-dfb8-4f07-9f61-9f9d423678c8")
)
(fp_text user "${REFERENCE}"
(at 0 0 0)
(layer "F.Fab")
(uuid "cd6b3ce3-0520-4125-86bf-242ede129ff5")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(pad "1" smd roundrect
(at -2.25 0)
(size 2 2.8)
(layers "F.Cu" "F.Paste" "F.Mask")
(roundrect_rratio 0.25)
(uuid "3a77053f-47c3-4ce9-a55a-55a85019e072")
)
(pad "2" smd roundrect
(at 2.25 0)
(size 2 2.8)
(layers "F.Cu" "F.Paste" "F.Mask")
(roundrect_rratio 0.25)
(uuid "75aed92d-5743-48f8-b099-b6602d249a7c")
)
(model "${KIPRJMOD}/CM5IO.3dshapes/SRP5030CC.stp"
(offset
(xyz 0 0 0)
)
(scale
(xyz 1 1 1)
)
(rotate
(xyz 0 0 0)
)
)
)

997
refs/CM5IO.pretty/M.2 M Key socket.kicad_mod Normal file
View File

@@ -0,0 +1,997 @@
(footprint "M.2 M Key socket"
(version 20240108)
(generator "pcbnew")
(generator_version "8.0")
(layer "F.Cu")
(property "Reference" "REF**"
(at -7.62 -10.287 0)
(layer "F.SilkS")
(uuid "870c1bf4-cdb9-4e51-bd37-a1b37e730674")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Value" "M.2 M Key socket"
(at 2.54 -8.255 0)
(layer "F.Fab")
(uuid "debde141-a1ed-4b9e-9942-71d9b9bb178f")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Footprint" "M.2 M Key socket"
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "ad24f8e2-fe05-47e3-98c8-6efae35d11a2")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Datasheet" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "a14e199f-f449-4c98-b7fd-92cdf31cd585")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Description" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "67a67510-14b2-49f5-8ae0-a18bcc702033")
(effects
(font
(size 1.27 1.27)
)
)
)
(fp_line
(start -11.5 0)
(end -11.5 78.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "e86241e9-7039-4351-974e-0a752ffb463b")
)
(fp_line
(start -11.5 28.25)
(end -4 28.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "605d1df6-24da-4980-8503-3f495bd1a5e2")
)
(fp_line
(start -11.5 40.25)
(end -4 40.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "f44acbf7-5377-419c-9bcf-339c62666c6d")
)
(fp_line
(start -11.5 58.25)
(end -4 58.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "13c75ace-037c-4540-a9ec-fa31735d33e9")
)
(fp_line
(start -11.5 78.25)
(end -4 78.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "594a1aa4-00fc-429b-a6cb-36d4174553bf")
)
(fp_line
(start -11 2.48)
(end -11 -2.805)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "6e8ae963-3315-4d8e-90c3-eda60b30a24d")
)
(fp_line
(start -9.47 2.48)
(end -11 2.48)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "b1a248db-2621-421d-a2bf-f30505430715")
)
(fp_line
(start 4 28.25)
(end 11.5 28.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "3d09cc5b-e2d7-40cf-811e-d431138c9855")
)
(fp_line
(start 4 40.25)
(end 11.5 40.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "c66c2f3e-e6a6-4df4-9d02-7f82d4d3cc55")
)
(fp_line
(start 4 58.25)
(end 11.5 58.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "6fd18eef-4c91-4bc6-839c-d5429b4db7bc")
)
(fp_line
(start 4 78.25)
(end 11.5 78.25)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "ea8a9c84-bcd0-4c8f-a292-2860051db377")
)
(fp_line
(start 5.2135 -5.7)
(end 6.7765 -5.7)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "16c73f5b-73ea-443d-a32e-0cf318146ac7")
)
(fp_line
(start 5.4635 2.48)
(end 7.0265 2.48)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "b2b8636c-1c76-4f48-85cd-b5c7566bc9e5")
)
(fp_line
(start 11 -2.805)
(end 11 -1.145)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "5946172a-554f-490d-a484-a40c0a88af8d")
)
(fp_line
(start 11 2.48)
(end 9.47 2.48)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "da29f8c8-552e-451c-88ee-d2e8ac257f32")
)
(fp_line
(start 11 2.48)
(end 11 1.145)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "4d1dff5e-f886-4806-825a-57fbf67dbcac")
)
(fp_line
(start 11.5 78.25)
(end 11.5 0)
(stroke
(width 0.1)
(type default)
)
(layer "F.SilkS")
(uuid "3c58f8aa-8309-4196-bde9-b1f8179c0989")
)
(fp_circle
(center -9.25 -6.796)
(end -9.15 -6.796)
(stroke
(width 0.2)
(type solid)
)
(fill none)
(layer "F.SilkS")
(uuid "4bc53744-def2-43a5-8617-023479778c1f")
)
(fp_line
(start -11.25 -6.3)
(end -11.25 3.3)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "0dc48f72-db70-415e-97d4-43e08a5f0c68")
)
(fp_line
(start -11.25 3.3)
(end 11.25 3.3)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "94c281a6-058c-4d4e-ad3c-23276bb1cfaa")
)
(fp_line
(start 11.25 -6.3)
(end -11.25 -6.3)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "5bcbcded-c231-48b6-aaf1-b10be41ff3a4")
)
(fp_line
(start 11.25 3.3)
(end 11.25 -6.3)
(stroke
(width 0.05)
(type solid)
)
(layer "F.CrtYd")
(uuid "7180e7c7-19c0-425d-8bfd-74d65fe56599")
)
(fp_line
(start -11 -5.7)
(end 11 -5.7)
(stroke
(width 0.127)
(type solid)
)
(layer "F.Fab")
(uuid "a2b7789d-04d2-4259-88dc-493990bc269a")
)
(fp_line
(start -11 2.48)
(end -11 -5.7)
(stroke
(width 0.127)
(type solid)
)
(layer "F.Fab")
(uuid "00fc249f-4c56-472e-94ff-5ad9f5cb97c6")
)
(fp_line
(start 11 -5.7)
(end 11 2.48)
(stroke
(width 0.127)
(type solid)
)
(layer "F.Fab")
(uuid "b45b7e4b-0eef-4bbe-a74f-89845df5f2ca")
)
(fp_line
(start 11 2.48)
(end -11 2.48)
(stroke
(width 0.127)
(type solid)
)
(layer "F.Fab")
(uuid "1ea253e7-3e42-4757-85bd-2530c3932a28")
)
(fp_circle
(center -9.25 -6.796)
(end -9.15 -6.796)
(stroke
(width 0.2)
(type solid)
)
(fill none)
(layer "F.Fab")
(uuid "aa978133-4db1-4dfb-b0a3-903ea251e8d6")
)
(fp_text user "2280"
(at 10 76.25 180)
(unlocked yes)
(layer "F.SilkS")
(uuid "36aa1015-39c9-4e63-a78e-3e4e8781b3b2")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2230"
(at 10 28.75 180)
(unlocked yes)
(layer "F.SilkS")
(uuid "4ce6f1f0-c8fd-43dd-9dfc-8eaa85350299")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "M.2 M Key"
(at -3.9 5.5 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "71fbe4fd-8d7c-440b-94bf-6dcef6e854ea")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2280"
(at -10 77.75 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "72210e5b-976f-4733-b828-b9d8910b254f")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2242"
(at 10 40.75 180)
(unlocked yes)
(layer "F.SilkS")
(uuid "782f7b38-d6c2-4d4a-aed4-7457839e41b3")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2260"
(at -10 57.75 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "7e3d3f21-a2df-4171-b934-16c478156e07")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2230"
(at -9.75 27.75 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "a963592d-dcc5-4ce7-abdf-030d1ef8fd59")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2260"
(at 10 58.75 180)
(unlocked yes)
(layer "F.SilkS")
(uuid "bac7ca2b-c525-4e28-ab9b-2c8593adde2c")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(fp_text user "2242"
(at -10 39.75 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "bb74da0c-132b-4cf6-8fa1-535334880b03")
(effects
(font
(size 1 1)
(thickness 0.1)
)
(justify left bottom)
)
)
(pad "" np_thru_hole circle
(at -10 0)
(size 1.15 1.15)
(drill 1.15)
(layers "*.Cu" "*.Mask")
(uuid "057dfbef-8f9a-4a8a-86c6-a4431606f236")
)
(pad "" np_thru_hole circle
(at 10 0)
(size 1.65 1.65)
(drill 1.65)
(layers "*.Cu" "*.Mask")
(uuid "317402fd-5c01-4ca5-ad0b-32794ece82ba")
)
(pad "1" smd rect
(at -9.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "d1ff2b98-73a0-4d2c-b638-5d66831840bb")
)
(pad "2" smd rect
(at -9 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "8e229cb3-ccb8-43ca-9a4c-7809fbcf9d99")
)
(pad "3" smd rect
(at -8.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "92406c1a-c40e-4a1e-9146-185fe920d6e0")
)
(pad "4" smd rect
(at -8.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "ee078aba-0dd8-4f19-bf3c-5cc006d05aac")
)
(pad "5" smd rect
(at -8.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "031a4b25-1d13-49b1-8d24-2d5e723f8203")
)
(pad "6" smd rect
(at -8 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "9f3c1e09-198d-4731-82d7-8569c520f596")
)
(pad "7" smd rect
(at -7.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "b8a677b8-3456-4a44-af5f-dc571084168f")
)
(pad "8" smd rect
(at -7.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "a29d5beb-f876-4119-b780-32e1854c54f2")
)
(pad "9" smd rect
(at -7.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "8ec9fae1-4ba2-45fb-8a9d-2cfb68e80129")
)
(pad "10" smd rect
(at -7 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "ed48c46d-903e-4f0b-ad4e-bdf0178fb022")
)
(pad "11" smd rect
(at -6.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "8f71dd9e-3c30-47d7-8e89-42c0c179981c")
)
(pad "12" smd rect
(at -6.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "d8df4b78-d6d5-4eaf-bd5d-9231589f93d0")
)
(pad "13" smd rect
(at -6.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "326fe665-053d-48ea-b5bb-3a4be450edf9")
)
(pad "14" smd rect
(at -6 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "f06339fd-1163-48e2-9c69-8433b8d30936")
)
(pad "15" smd rect
(at -5.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "f878e85a-8f6f-4dee-bc17-5e67db68840c")
)
(pad "16" smd rect
(at -5.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "482d078b-67bd-4b9a-9fe6-bda5d26c101f")
)
(pad "17" smd rect
(at -5.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "a14e6288-fb57-40f4-9715-7003215dd837")
)
(pad "18" smd rect
(at -5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "24883f65-9899-4f1b-b492-15feead91ab1")
)
(pad "19" smd rect
(at -4.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "251c6224-4753-4052-8052-e7a0f4171d31")
)
(pad "20" smd rect
(at -4.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "befba2cc-c4fc-4850-b2cd-873df5103776")
)
(pad "21" smd rect
(at -4.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "0b3b501e-3bed-4888-801a-3b5447fb024a")
)
(pad "22" smd rect
(at -4 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "224bfde7-dde7-4b11-91f2-166487f6231d")
)
(pad "23" smd rect
(at -3.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "c054c638-1f85-4897-90d8-beece7261c60")
)
(pad "24" smd rect
(at -3.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "7d0048fa-06ef-453b-b446-1f812615c480")
)
(pad "25" smd rect
(at -3.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "1637dc00-c8b1-4645-b15f-f0879a039909")
)
(pad "26" smd rect
(at -3 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "828dc527-a769-4bf4-94c9-61c4eb265def")
)
(pad "27" smd rect
(at -2.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "98a9a491-8058-4dd1-b9d1-837e1aee66cb")
)
(pad "28" smd rect
(at -2.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "ccdab5f8-86f9-4274-8457-89a23a4afe69")
)
(pad "29" smd rect
(at -2.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "3fda1d6b-fb43-4168-a79d-e7a21643cb34")
)
(pad "30" smd rect
(at -2 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "1f666d65-a8ca-46f0-bf93-7ba8f6f9fcad")
)
(pad "31" smd rect
(at -1.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "ed6807ec-7adf-414a-bfbf-904eff02c536")
)
(pad "32" smd rect
(at -1.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "85b25c2e-0892-4eb1-b7cc-787c2ef46d83")
)
(pad "33" smd rect
(at -1.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "78e9974a-ada7-423f-a170-23c78bc1698f")
)
(pad "34" smd rect
(at -1 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "a8575487-1c36-4889-bb83-34ac55825a33")
)
(pad "35" smd rect
(at -0.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "8c1acea8-5046-4d6f-ae2d-775f7e4f80f4")
)
(pad "36" smd rect
(at -0.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "7c2dbd61-7905-40c1-9c0b-b9ea88360ea8")
)
(pad "37" smd rect
(at -0.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "e80ddf72-f085-4a18-b46c-262dd4cfad15")
)
(pad "38" smd rect
(at 0 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "61b40255-73e1-4fa0-91a2-f5529e0de601")
)
(pad "39" smd rect
(at 0.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "c9078cd1-9a17-47e7-b452-a39573f4e711")
)
(pad "40" smd rect
(at 0.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "06f4cd4e-8546-480b-892d-cf49a5d77d55")
)
(pad "41" smd rect
(at 0.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "2779f992-a104-454a-8b0b-cff85d775601")
)
(pad "42" smd rect
(at 1 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "3fab9ef7-ef1f-4aa3-b500-9aba4dccac9b")
)
(pad "43" smd rect
(at 1.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "1fc42491-e603-46c5-b131-24f85d53a451")
)
(pad "44" smd rect
(at 1.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "bb3079df-b131-426d-95a0-677f0bc4b013")
)
(pad "45" smd rect
(at 1.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "e62c47e2-bc85-4c8c-aa17-2c4516c76917")
)
(pad "46" smd rect
(at 2 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "c04be3e7-5d0a-4bd7-b785-f21fe6291a91")
)
(pad "47" smd rect
(at 2.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "126388aa-afac-4652-82c5-4e1ca22bb1c3")
)
(pad "48" smd rect
(at 2.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "986214bd-c8b2-4ae1-a44d-28b36da4e0a2")
)
(pad "49" smd rect
(at 2.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "b2a4be12-034a-4e2f-a098-5904ebab2b7d")
)
(pad "50" smd rect
(at 3 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "6b12ece5-b132-4a19-9ce5-8affd9b8fd24")
)
(pad "51" smd rect
(at 3.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "cda43d5c-f02c-48be-ba5d-0431c67cf994")
)
(pad "52" smd rect
(at 3.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "5deefa4d-9f41-4f59-8957-2814caabf54f")
)
(pad "53" smd rect
(at 3.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "52774314-3d6d-489e-a11a-e9c75de6c763")
)
(pad "54" smd rect
(at 4 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "43160dd6-61b5-4690-8904-ee9ac2ff69c8")
)
(pad "55" smd rect
(at 4.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "e79a6c57-3869-42f7-9b97-3ec47affde9d")
)
(pad "56" smd rect
(at 4.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "d113fe64-48e2-49a5-8f2f-72f119a25590")
)
(pad "57" smd rect
(at 4.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "f5337a02-5a05-401e-980e-f312245dbc15")
)
(pad "58" smd rect
(at 5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "51a9a2e7-9c72-442c-b7a4-78c1bfeac1fc")
)
(pad "67" smd rect
(at 7.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "66c8188c-4778-4211-a03b-ee62b65d2d3b")
)
(pad "68" smd rect
(at 7.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "468504c7-e274-4a26-88ca-10cb1eae9711")
)
(pad "69" smd rect
(at 7.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "1ee95418-19d5-42eb-a684-05ae0c4f4f77")
)
(pad "70" smd rect
(at 8 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "a27e4bf4-879c-4b9a-8db6-a1daa9d7eb40")
)
(pad "71" smd rect
(at 8.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "139d8f65-140c-48b5-b781-69131de86618")
)
(pad "72" smd rect
(at 8.5 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "6bee27b6-40c6-402d-8d3c-caf12795a053")
)
(pad "73" smd rect
(at 8.75 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "56177229-8378-496e-98cd-98cb371e968e")
)
(pad "74" smd rect
(at 9 2.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "079a1324-c94c-4972-9225-0419a25d0be0")
)
(pad "75" smd rect
(at 9.25 -5.275)
(size 0.3 1.55)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "2d5cc328-2073-4451-9b68-e3caf7939dd1")
)
(pad "M1" thru_hole circle
(at 0 28.25)
(size 5.8 5.8)
(drill 3.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(solder_mask_margin 0.2)
(uuid "2f79c99d-8e33-483c-b9b8-a9ac48ab04f0")
)
(pad "M2" thru_hole circle
(at 0 40.25)
(size 5.8 5.8)
(drill 3.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(solder_mask_margin 0.2)
(uuid "38e1a50c-b6a5-477f-a18f-4c4598a553c2")
)
(pad "M3" thru_hole circle
(at 0 58.25)
(size 5.8 5.8)
(drill 3.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(solder_mask_margin 0.2)
(uuid "088a3ef9-39b1-4e37-94f5-535ce6532672")
)
(pad "M4" thru_hole circle
(at 0 78.25)
(size 5.8 5.8)
(drill 3.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(solder_mask_margin 0.2)
(uuid "ddc04b3e-0dc0-4737-ba3b-ddae4dac72dc")
)
(pad "S1" smd rect
(at -10.35 -4.5)
(size 1.2 2.75)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "d1d3bee1-6d71-4726-b70c-dc7d013a3320")
)
(pad "S2" smd rect
(at 10.35 -4.5)
(size 1.2 2.75)
(layers "F.Cu" "F.Paste" "F.Mask")
(solder_mask_margin 0.102)
(uuid "aef73218-bc2d-43fa-b3eb-23959e67d223")
)
(model "${KIPRJMOD}/CM5IO.3dshapes/MTSSD03-67MSW337.STEP"
(offset
(xyz 0 1.8 1.3)
)
(scale
(xyz 1 1 1)
)
(rotate
(xyz 90 -180 -90)
)
)
)

348
refs/CM5IO.pretty/MTCONN_UBAF30-D2011.kicad_mod Normal file
View File

@@ -0,0 +1,348 @@
(footprint "MTCONN_UBAF30-D2011"
(version 20240108)
(generator "pcbnew")
(generator_version "8.0")
(layer "F.Cu")
(descr "USB3 Stacked type A socket")
(tags "USB3 TypeA")
(property "Reference" "REF**"
(at 0 -0.5 0)
(unlocked yes)
(layer "F.SilkS")
(uuid "159e0420-4325-4168-86b6-a228ae385b74")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Value" "MTCONN_UBAF30-D2011"
(at 0 1 0)
(unlocked yes)
(layer "F.Fab")
(uuid "030d9eed-d060-4fb7-a3e5-dd631c9878c2")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(property "Footprint" "MTCONN_UBAF30-D2011"
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "ef8a18e9-0883-48e2-8681-d9035c0f4a3e")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Datasheet" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "ef5e3cea-3b46-42f1-a71e-6619c5c184ad")
(effects
(font
(size 1.27 1.27)
)
)
)
(property "Description" ""
(at 0 0 0)
(unlocked yes)
(layer "F.Fab")
(hide yes)
(uuid "64766762-f58d-495a-8fe2-957f1bc32c95")
(effects
(font
(size 1.27 1.27)
)
)
)
(attr through_hole)
(fp_line
(start -6.89 -7.86)
(end 6.89 -7.86)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "1aaca878-b95d-40c0-a6e7-e51d7ea87a6c")
)
(fp_line
(start -6.89 9.64)
(end -6.89 2)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "2e8f5299-7f88-46a5-a8cb-1a0fed2366f9")
)
(fp_line
(start -6.89 9.64)
(end 6.89 9.64)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "57e0bd81-dcb8-4586-9f3d-f7fad7eb46f9")
)
(fp_line
(start 6.89 2)
(end 6.89 9.64)
(stroke
(width 0.12)
(type solid)
)
(layer "F.SilkS")
(uuid "be9518e5-64b7-488c-b8e0-57dbc0b31ecf")
)
(fp_line
(start -6.89 -7.86)
(end -6.89 9.64)
(stroke
(width 0.12)
(type solid)
)
(layer "F.CrtYd")
(uuid "ed80fa79-747c-43b5-9b38-fb5bd42e26f7")
)
(fp_line
(start -6.89 9.64)
(end 6.89 9.64)
(stroke
(width 0.12)
(type solid)
)
(layer "F.CrtYd")
(uuid "c0dacdc1-bf02-49df-9de9-fb872c40583a")
)
(fp_line
(start 6.89 -7.86)
(end -6.89 -7.86)
(stroke
(width 0.12)
(type solid)
)
(layer "F.CrtYd")
(uuid "8cd79c52-f48b-4e66-a52b-72a42cc9b835")
)
(fp_line
(start 6.89 9.64)
(end 6.89 -7.86)
(stroke
(width 0.12)
(type solid)
)
(layer "F.CrtYd")
(uuid "7e13241e-25aa-48d7-8150-c41ff27ccc60")
)
(fp_text user "${REFERENCE}"
(at 0 2.5 0)
(unlocked yes)
(layer "F.Fab")
(uuid "fb08ffad-6464-4b99-bca1-78f476d9fe28")
(effects
(font
(size 1 1)
(thickness 0.15)
)
)
)
(pad "10" thru_hole circle
(at -6.57 -5.68)
(size 3.1 3.1)
(drill 2.3)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "bb9918bd-f910-4902-ae20-97a3e82279c6")
)
(pad "10" thru_hole circle
(at -6.57 0)
(size 3.1 3.1)
(drill 2.3)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "123c45e8-8d30-431c-9aba-0a7ac963657a")
)
(pad "10" thru_hole circle
(at 6.57 -5.68)
(size 3.1 3.1)
(drill 2.3)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "198bdd97-4623-4da9-8a84-0734fe1062a4")
)
(pad "10" thru_hole circle
(at 6.57 0)
(size 3.1 3.1)
(drill 2.3)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "ca8e5715-c125-44c3-9def-e42736e52986")
)
(pad "A1" thru_hole circle
(at -3.5 -2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "d24ba20f-b5c5-46a6-acbe-e1d66cd453f3")
)
(pad "A2" thru_hole circle
(at -1 -2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "318fee4e-d435-4430-a906-50f9661f31e4")
)
(pad "A3" thru_hole circle
(at 1 -2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "def50e31-8215-4c92-94e7-1aa356c381da")
)
(pad "A4" thru_hole circle
(at 3.5 -2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "93613739-6dd7-41f2-93cc-ca47ef8f1524")
)
(pad "A5" thru_hole circle
(at 4 -3.5)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "baceeda7-bade-4256-8bbb-c28f24f4ed4f")
)
(pad "A6" thru_hole circle
(at 2 -3.5)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "a5103b18-1ab3-4c42-a2a8-a012dcc97ba9")
)
(pad "A7" thru_hole circle
(at 0 -3.5)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "a4630606-90f5-48f4-b947-2b116f3c305c")
)
(pad "A8" thru_hole circle
(at -2 -3.55)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "b95e4631-c4e4-4f3f-bb43-563701a5cf2c")
)
(pad "A9" thru_hole circle
(at -4 -3.5)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "a0d2d040-4f0a-4784-b768-cf0168224cc0")
)
(pad "B1" thru_hole circle
(at -3.5 -5.2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "9b5ced6a-fbec-4cd9-a3eb-b178c0b3e470")
)
(pad "B2" thru_hole circle
(at -1 -5.2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "32f8e1ec-e58b-4513-8a59-443ac2bcbedd")
)
(pad "B3" thru_hole circle
(at 1 -5.2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "f50ee2b6-ebf4-4e4e-be8d-4d16045d962d")
)
(pad "B4" thru_hole circle
(at 3.5 -5.2)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "c097ec24-fe9e-4d95-aa42-d6a7782bcaf1")
)
(pad "B5" thru_hole circle
(at 4 -6.7)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "9f4d9b10-b0ee-43e0-98b1-7b6189db7ee7")
)
(pad "B6" thru_hole circle
(at 2 -6.7)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "5a22bd4a-ac05-446f-87ba-ac485a78e924")
)
(pad "B7" thru_hole circle
(at 0 -6.7)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "e20a5ea4-e4eb-49a0-a32f-03c3d6b4ce25")
)
(pad "B8" thru_hole circle
(at -2 -6.75)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "2b9dcb68-55a6-4469-99c6-e7842323b544")
)
(pad "B9" thru_hole circle
(at -4 -6.7)
(size 1.1 1.1)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "c023e606-9337-46f2-b835-98b4401d6a0a")
)
(model "${KIPRJMOD}/CM5IO.3dshapes/USB3stacked.STEP"
(offset
(xyz 0 -0.6 8.5)
)
(scale
(xyz 1 1 1)
)
(rotate
(xyz -90 0 0)
)
)
)

24
refs/CM5IO.pretty/MountingHole_2.7mm_M2.5_DIN965.kicad_mod Normal file
View File

@@ -0,0 +1,24 @@
(footprint "MountingHole_2.7mm_M2.5_DIN965" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "Mounting Hole 2.7mm, no annular, M2.5, DIN965")
(tags "mounting hole 2.7mm no annular m2.5 din965")
(attr exclude_from_pos_files exclude_from_bom)
(fp_text reference "REF**" (at 0 -3.35) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp b8c057d5-dc17-453d-912f-05b30d7e612e)
)
(fp_text value "MountingHole_2.7mm_M2.5_DIN965" (at 0 3.35) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 1a1b385a-cb8d-4557-99fd-e5782d36c05f)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp e08aae11-f655-4941-b438-d9802e1d4b1f)
)
(fp_circle (center 0 0) (end 2.35 0)
(stroke (width 0.15) (type solid)) (fill none) (layer "Cmts.User") (tstamp 66aea7f3-1bbe-4964-a920-8bc4d04f21ec))
(fp_circle (center 0 0) (end 2.6 0)
(stroke (width 0.05) (type solid)) (fill none) (layer "F.CrtYd") (tstamp 88f42438-87c5-4c9d-966a-6d3ad861acc9))
(pad "" np_thru_hole circle (at 0 0) (size 2.7 2.7) (drill 2.7) (layers "F&B.Cu" "*.Mask")
(solder_mask_margin 1.3) (clearance 1.3) (tstamp 7388b760-277c-4b82-bf7a-9ed81224c843))
)

1644
refs/CM5IO.pretty/Raspberry-Pi-5-Compute-Module.kicad_mod Normal file
View File

File diff suppressed because it is too large Load Diff

163
refs/CM5IO.pretty/SDCARD_MOLEX_503398-1892.kicad_mod Normal file
View File

@@ -0,0 +1,163 @@
(footprint "SDCARD_MOLEX_503398-1892" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(attr smd)
(fp_text reference "REF**" (at -3.907665 -8.415745) (layer "F.SilkS")
(effects (font (size 1.000685 1.000685) (thickness 0.015)))
(tstamp 0f339086-d5b9-4f19-8a90-09fe14f5e926)
)
(fp_text value "SDCARD_MOLEX_503398-1892" (at 3.719055 8.349145) (layer "F.Fab")
(effects (font (size 1.001094 1.001094) (thickness 0.015)))
(tstamp 31a140ac-66da-4500-9ad4-3f65578a4266)
)
(fp_line (start -6.55 -7.025) (end 6.55 -7.025)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 283622d9-d9d1-4943-8332-93bcf15c1188))
(fp_line (start -6.55 -4.325) (end -6.55 -1.425)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 8104d3f5-5c26-4953-9ef4-2e63cf4aab50))
(fp_line (start -6.55 1.575) (end -6.55 3.675)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 4df2cb2e-42f0-4e3c-b4ea-81dee6c9e25b))
(fp_line (start -5.876 7.025) (end -4.874 7.025)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp ffe25dc6-8f6a-450d-b87b-1fb56850dcb7))
(fp_line (start 0.874 7.025) (end 5.876 7.025)
(stroke (width 0.127) (type solid)) (layer "F.SilkS") (tstamp 7e97a101-8d4f-4c34-bb94-60b7922c20f6))
(fp_circle (center -3.4 -5.6) (end -3.3 -5.6)
(stroke (width 0.2) (type solid)) (fill none) (layer "F.SilkS") (tstamp 080b30fe-d08f-4bc5-9dd0-a669464be986))
(fp_line (start -4.67 -9.33) (end -4.67 -7.28)
(stroke (width 0.12) (type solid)) (layer "Dwgs.User") (tstamp 882d0eef-72c2-4a8a-99d3-66f6abfa5ea1))
(fp_line (start -4.67 -9.33) (end 6.33 -9.33)
(stroke (width 0.12) (type solid)) (layer "Dwgs.User") (tstamp b4f3fe80-2d70-47db-a350-15815d84ccd7))
(fp_line (start -4.67 -7.93) (end 6.33 -7.93)
(stroke (width 0.12) (type solid)) (layer "Dwgs.User") (tstamp 42b9e5a0-803e-4600-96fd-4e78e76b2675))
(fp_line (start 0.83 -6.7) (end 0.83 -9.33)
(stroke (width 0.12) (type solid)) (layer "Dwgs.User") (tstamp aaef2e67-37a1-4b92-8821-211adb6f66ed))
(fp_line (start 6.33 -9.33) (end 6.33 -7.35)
(stroke (width 0.12) (type solid)) (layer "Dwgs.User") (tstamp e753b2dd-fcfa-4159-a6c9-b0e643891be2))
(fp_poly
(pts
(xy -6.84156 -1.125)
(xy -6.13 -1.125)
(xy -6.13 1.27716)
(xy -6.84156 1.27716)
)
(stroke (width 0.01) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp dde6b96c-98e9-42d3-a20f-4ee91ab2bf46))
(fp_poly
(pts
(xy -6.83634 -1.125)
(xy -6.13 -1.125)
(xy -6.13 1.27618)
(xy -6.83634 1.27618)
)
(stroke (width 0.01) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp ea88e8af-334b-418b-a478-fbd1dbcdc91f))
(fp_poly
(pts
(xy -5.24526 4.575)
(xy -4.685 4.575)
(xy -4.685 6.73818)
(xy -5.24526 6.73818)
)
(stroke (width 0.01) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 2fa1d07f-750e-46fe-8454-0083dc2187c0))
(fp_poly
(pts
(xy -5.23866 4.575)
(xy -4.685 4.575)
(xy -4.685 6.72971)
(xy -5.23866 6.72971)
)
(stroke (width 0.01) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 49187462-d679-416b-8e01-b46ba56ec805))
(fp_poly
(pts
(xy -3.22541 6.375)
(xy -2.67 6.375)
(xy -2.67 6.93664)
(xy -3.22541 6.93664)
)
(stroke (width 0.01) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp c538d7dc-9e33-4d6b-9e1e-e3143aed9267))
(fp_poly
(pts
(xy -3.22251 6.375)
(xy -2.67 6.375)
(xy -2.67 6.9304)
(xy -3.22251 6.9304)
)
(stroke (width 0.01) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 61d9576d-7191-459c-a6fd-a8ceb0fb0b76))
(fp_poly
(pts
(xy -3.17 -3.725)
(xy -3.17 1.275)
(xy -3.82 1.275)
(xy -3.82 3.875)
(xy 0.57 3.875)
(xy 0.57 5.125)
(xy -1.73 5.125)
(xy -1.73 7.305)
(xy -0.43 7.305)
(xy -0.43 6.525)
(xy 6.13 6.525)
(xy 6.13 3.975)
(xy 6.83 3.975)
(xy 6.83 -3.725)
)
(stroke (width 0.0001) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 165d3a49-35d1-43a4-826e-9fab76fa70be))
(fp_poly
(pts
(xy -3.17 -3.725)
(xy -3.17 1.275)
(xy -3.82 1.275)
(xy -3.82 3.875)
(xy 0.57 3.875)
(xy 0.57 5.125)
(xy -1.73 5.125)
(xy -1.73 7.305)
(xy -0.43 7.305)
(xy -0.43 6.525)
(xy 6.13 6.525)
(xy 6.13 3.975)
(xy 6.83 3.975)
(xy 6.83 -3.725)
)
(stroke (width 0.0001) (type solid)) (fill solid) (layer "Dwgs.User") (tstamp 23a4bd5d-4a09-4860-8bd4-da92b40739dc))
(fp_line (start -7 -7.25) (end 7 -7.25)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp a635dc1c-33e4-4cd8-9b67-4fe0cd640816))
(fp_line (start -7 7.5) (end -7 -7.25)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp dd944f35-521d-4d2e-b041-2a6c39582454))
(fp_line (start 7 -7.25) (end 7 7.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e7d51882-be9f-4a32-b6ab-0995b5c3d191))
(fp_line (start 7 7.5) (end -7 7.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b061c18c-8287-4038-9b34-dfc2ef97d5f0))
(fp_line (start -6.55 -7.025) (end 6.55 -7.025)
(stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp f25635e3-a8c1-444e-83a3-16325471db4c))
(fp_line (start -6.55 7.025) (end -6.55 -7.025)
(stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp 02a43fc3-0592-4d2f-b89e-f2889f9c8848))
(fp_line (start 6.55 -7.025) (end 6.55 7.025)
(stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp e02df805-1a3f-4112-a7ff-30b8e700f4e0))
(fp_line (start 6.55 7.025) (end -6.55 7.025)
(stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp 0723ac9f-9379-45c3-983a-bd09d8559b7c))
(fp_circle (center -2.38 -5.775) (end -2.28 -5.775)
(stroke (width 0.2) (type solid)) (fill none) (layer "F.Fab") (tstamp 072e45bc-e164-4d2d-83e9-7919d68a606f))
(pad "1" smd rect (at -2.38 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 197602f0-198a-4dc4-9267-3de393666103))
(pad "2" smd rect (at -1.28 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 0a84c92a-ae37-4a0c-8fc2-706db4625c95))
(pad "3" smd rect (at -0.18 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a3c779a0-8683-4abb-a732-bf22ac0c0f18))
(pad "4" smd rect (at 0.92 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5b89f47a-43bc-48cc-8295-e2330a1a1f51))
(pad "5" smd rect (at 2.02 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2b1ad851-5ad7-48d0-9d78-370fb14807d3))
(pad "6" smd rect (at 3.12 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e09e7ae4-38d1-4fcb-987d-318b6ff55e31))
(pad "7" smd rect (at 4.22 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c0610bee-6818-4575-a0ce-6ee5b3b3e623))
(pad "8" smd rect (at 5.32 -5.625) (size 0.7 1.1) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 623d747f-e536-407d-8b07-8ad6ff9d4d4a))
(pad "9" smd rect (at -4.17 6.84) (size 0.9 0.93) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f1ddd374-7998-4942-b4a5-a8dcf9c84254))
(pad "10" smd rect (at 0.095 6.915) (size 1.05 0.78) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b0193119-64bb-4901-86e0-5df58c7e13b5))
(pad "11" smd rect (at -6.48 5.64) (size 0.7 3.33) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d15b5e1f-a72e-42da-ba36-10499ebab43a))
(pad "11" smd rect (at -6.26 -5.61) (size 1.14 1.83) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bb96a903-82a3-4c19-b50f-1445e5a20c98))
(pad "11" smd rect (at 6.4 -5.125) (size 0.86 2.8) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1f3a54d4-5d28-42d8-89c7-bd0132a0e149))
(pad "11" smd rect (at 6.48 5.64) (size 0.7 3.33) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b5d04279-8975-461b-a463-a15e3f410a4e))
(model "${KIPRJMOD}/CM5IO.3dshapes/5033981892.stp"
(offset (xyz -135.9 -16.4 154.4))
(scale (xyz 1 1 1))
(rotate (xyz 180 0 0))
)
)

95
refs/CM5IO.pretty/TRJG0926HENL.kicad_mod Normal file
View File

@@ -0,0 +1,95 @@
(footprint "TRJG0926HENL" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "https://p.globalsources.com/IMAGES/PDT/SPEC/690/K1160305690.pdf")
(tags "RJ45 Magjack")
(attr through_hole)
(fp_text reference "REF**" (at 0.01 -11.32) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 705b382b-ff69-413e-84e6-0fd86757e863)
)
(fp_text value "TRJG0926HENL" (at 0 11.58) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 20be6db7-13e5-4234-90c4-c6907cf27ae1)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5b57542e-00f6-4cfc-91ee-fb8c112e69a3)
)
(fp_line (start -8.12 -10.62) (end -8.12 -4.71)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 680bcfbc-8d22-42a7-9469-e143f63c66a3))
(fp_line (start -8.12 -10.62) (end 8.12 -10.62)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 0fdb7160-093d-4a2c-b77c-ab3a60de0bb8))
(fp_line (start -8.12 -1.43) (end -8.12 11.02)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 677dc7fa-aae9-4dd6-9915-d913747c7be3))
(fp_line (start -8 10.75) (end -8.25 10.75)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 2aa1ce7c-e3a0-40a1-89d3-85fd31728146))
(fp_line (start -7.9 10.9) (end -7.9 11.15)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a4c46ab4-a7ae-48a5-a46b-bd56a72e3c62))
(fp_line (start 8.12 -10.62) (end 8.12 -4.71)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 07612761-ed8b-48b5-881a-6d5cee3600ba))
(fp_line (start 8.12 -1.43) (end 8.12 11.02)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 5cec026a-8112-4044-a2e6-e32165ec71e2))
(fp_line (start 8.12 11.02) (end -8.12 11.02)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f1bbc89a-495b-4371-a53b-1e156b0fe8d2))
(fp_line (start -9.25 -2.43) (end -9.25 -3.71)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f06c3d8e-f223-466f-ba23-cb4e57155dff))
(fp_line (start -9.25 -2.43) (end -8.25 -1.43)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 5119cc08-eb1a-4131-ad3b-90c78c428f3d))
(fp_line (start -8.25 -10.75) (end 8.25 -10.75)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b24f3d55-27f1-4b6a-a779-af6c34ada038))
(fp_line (start -8.25 -4.71) (end -9.25 -3.71)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d416bd15-ea52-45f4-bcbf-48f6f2d9abf7))
(fp_line (start -8.25 -4.71) (end -8.25 -10.75)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 76ee8bcc-33cd-448e-97d8-95057e346216))
(fp_line (start -8.25 -1.43) (end -8.25 11.15)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp c0feb834-ae54-4501-9dff-aed9b5246431))
(fp_line (start -8.25 11.15) (end 8.25 11.15)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d6c3bb97-19b6-4d27-91bf-52e5b8616d48))
(fp_line (start 8.25 -4.71) (end 8.25 -10.75)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 00734c9b-0a9d-42dc-b699-4fa242299e0e))
(fp_line (start 8.25 -4.71) (end 9.25 -3.71)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b3ea7256-93bc-44f5-be21-d1ace0bd2e38))
(fp_line (start 8.25 -1.43) (end 8.25 11.15)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d7b3f670-318b-47ab-9335-6628a077c8df))
(fp_line (start 9.25 -2.43) (end 8.25 -1.43)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 1e2f39ee-6945-4717-9fab-fc01eb1b67a7))
(fp_line (start 9.25 -2.43) (end 9.25 -3.71)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp d161c5cb-7406-4c7e-8197-264e5f4a1c4a))
(fp_line (start -8 -10.5) (end -8 0)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a5feb916-acae-472f-88e1-74e51d928e74))
(fp_line (start -8 -10.5) (end 8 -10.5)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 258800e2-1361-4ed3-b03e-cea862b6b12f))
(fp_line (start -8 -5.37) (end -8 10.9)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 4de77c6e-2d61-4c18-aad8-d827f0164b4a))
(fp_line (start -8 10.9) (end 8 10.9)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 381a83f5-3065-45a8-a79f-c434601f2701))
(fp_line (start 8 -10.5) (end 8 10.9)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 464d27b8-e4b0-47ba-9cdc-5d1c1ff088e0))
(pad "" np_thru_hole circle (at -5.715 0) (size 3.2 3.2) (drill 3.2) (layers "*.Cu" "*.Mask") (tstamp 2709183a-a686-45e9-9cb9-f8037f7fa8f3))
(pad "" np_thru_hole circle (at 5.715 0) (size 3.2 3.2) (drill 3.2) (layers "*.Cu" "*.Mask") (tstamp dd808b8f-0d74-4fc3-b38d-5cb7380c8a26))
(pad "1" thru_hole roundrect (at -5.715 -8.89) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.167) (tstamp 4bbdca2e-1700-4b42-af03-7322fcead74c))
(pad "2" thru_hole circle (at -4.445 -6.35) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp a1db1da7-05ef-4d7c-bf0e-4c0cb7f79819))
(pad "3" thru_hole circle (at -3.175 -8.89) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 1ccd7ea9-92b2-42ed-8848-5028a5af89ef))
(pad "4" thru_hole circle (at -1.905 -6.35) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 1a53e93d-1cf5-4654-a1d1-32ffc708d838))
(pad "5" thru_hole circle (at -0.635 -8.89) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp c2a2c3fb-4c24-4523-acb0-cfc01e4c3543))
(pad "6" thru_hole circle (at 0.635 -6.35 90) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 5d824785-caea-495b-ba61-b14e25f0cf31))
(pad "7" thru_hole circle (at 1.905 -8.89) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 42d18e79-3674-42cd-9cc8-7b9510be6f46))
(pad "8" thru_hole circle (at 3.175 -6.35) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 4d12951d-bf7b-4f07-af16-3da5a678f4ce))
(pad "9" thru_hole circle (at 4.445 -8.89) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp b570dd70-d0e0-480f-b783-f720c69681dc))
(pad "10" thru_hole circle (at 5.715 -6.35) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp b63704fb-a4f1-48d6-9bb9-2aa2c7420560))
(pad "11" thru_hole circle (at -5.715 -3.83) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp bbcfc3bd-7f63-4797-ae24-05f4ee20b4bf))
(pad "12" thru_hole circle (at -3.175 -2.56) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp f41410e0-b30e-478c-8395-94758b02f780))
(pad "13" thru_hole circle (at 3.175 -2.56) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp b0b75ac4-d2ee-4c3f-bbe3-fff032e7b53f))
(pad "14" thru_hole circle (at 5.715 -3.83) (size 1.5 1.5) (drill 0.9) (layers "*.Cu" "*.Mask") (tstamp 989a6b41-a40a-4945-8989-c2df752be7cb))
(pad "15" thru_hole circle (at -6.63 4.06) (size 1.5 1.5) (drill 1.02) (layers "*.Cu" "*.Mask") (tstamp ae8e8894-d222-4a3c-aead-6f18e16d9c00))
(pad "16" thru_hole circle (at -4.09 4.06) (size 1.5 1.5) (drill 1.02) (layers "*.Cu" "*.Mask") (tstamp 8c07df35-89b6-40a4-a7d9-1796e4b1c98d))
(pad "17" thru_hole circle (at 4.09 4.06) (size 1.5 1.5) (drill 1.02) (layers "*.Cu" "*.Mask") (tstamp d4872a15-646c-401a-8c2a-ab18855b1f9c))
(pad "18" thru_hole circle (at 6.63 4.06) (size 1.5 1.5) (drill 1.02) (layers "*.Cu" "*.Mask") (tstamp 69f2ea40-d7fc-4326-951c-feb03e3c4520))
(pad "19" thru_hole circle (at -7.875 -3.05) (size 2.5 2.5) (drill 1.7) (layers "*.Cu" "*.Mask") (tstamp 290360c5-e72c-49c7-b357-0ee46eebcdd5))
(pad "20" thru_hole circle (at 7.875 -3.05) (size 2.5 2.5) (drill 1.7) (layers "*.Cu" "*.Mask") (tstamp b6da9771-4617-45db-9811-02e044609eaf))
(model "${KIPRJMOD}/CM5IO.3dshapes/TRJG0926HENL .stp"
(offset (xyz 0 10.45 6.8))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)

36
refs/CM5IOBOM.txt Normal file
View File

@@ -0,0 +1,36 @@
"Id";"Designator";"Footprint";"Quantity";"Designation";"Supplier and ref";
1;"BT1";"BatteryHolder_Keystone_3034_1x20mm";1;"Battery_Cell";;;
2;"SW1";"SW_Tactile_SPST_Angled_PTS645Vx39-2LFS";1;"Right angle Tact button";;;
3;"C1,C12,C13,C10,C18,C9,C19";"C_0402_1005Metric";7;"100n";;;
4;"C5,C6,C16,C8,C2,C17,C7,C15,C14,C4";"C_0805_2012Metric";10;"10u";;;
5;"J5,J16";"Hirose_FH12-22S-0.5SH_1x22-1MP_P0.50mm_Horizontal";2;"Conn_01x22_Female";;;
6;"R10,R1,R17";"R_0402_1005Metric";3;"1k";;;
7;"U1,U2";"USON-10_2.5x1.0mm_P0.5mm";2;"TPD4EUSB30";;;
8;"U12";"TSOT-23_HandSoldering";1;"RT9742SNGV";;;
9;"J8";"PinHeader_2x20_P2.54mm_Vertical";1;"THD-20-R";;;
10;"D2,D3";"LED_0603_1608Metric";2;"LED Green";;;
11;"R3,R2";"R_0402_1005Metric";2;"470R";;;
12;"J9,J6";"PinHeader_2x02_P2.54mm_Vertical";2;"THD-02-R";;;
13;"J11";"USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal";1;"USB_C_Receptacle_USB2.0";;;
14;"D1";"LED_0603_1608Metric";1;"LED Red";;;
15;"U5";"SOT-353_SC-70-5";1;"74LVC1G07SE-7";;;
16;"U18";"SOT-23-5";1;"RT9742GGJ5";;;
17;"U3";"TRJG0926HENL";1;"MagJack-A70-112-331N126";;;
18;"J10,J22";"EDAC 690-019-298-412";2;"690-019-298-412";;;
19;"R6,R7,R8,R16";"R_0402_1005Metric";4;"2.2K 1%";;;
20;"J2";"PinHeader_2x07_P2.54mm_Vertical";1;"Conn_02x07_Odd_Even";;;
21;"R5";"R_0805_2012Metric_Pad1.20x1.40mm_HandSolder";1;"0R";;;
22;"U8";"DFN-8-1EP_2x2mm_P0.5mm_EP1.05x1.75mm";1;"AP3441SHE-7B";;;
23;"J7";"SDCARD_MOLEX_503398-1892";1;"Micro_SD_Card_Det";;;
24;"J4";"M.2 M Key socket";1;"Bus_M.2_Socket_M";;;
25;"C11";"C_0402_1005Metric";1;"4.7nF";;;
26;"J12";"MTCONN_UBAF30-D2011";1;"USB3_A";;;
27;"J14";"JST_SH_BM04B-SRSS-TB_1x04-1MP_P1.00mm_Vertical";1;"JST_SHBM04B-SRSS-TB";;;
28;"C3";"CP_EIA-7343-31_Kemet-D";1;"100uF";;;
29;"U7";"Crystal_SMD_3225-4Pin_3.2x2.5mm";1;"ASEK-32.768KHZ-L-R-T";;;
30;"U6";"SOT-23-6";1;"AP22653W6";;;
31;"L1";"L_Bourns_SRP5030CC";1;"2.2uH";;;
32;"R15";"R_0402_1005Metric";1;"10K 1%";;;
33;"R12";"R_0402_1005Metric";1;"15K 1%";;;
34;"R14";"R_0402_1005Metric";1;"100K 1%";;;
35;"Module1";"Raspberry-Pi-5-Compute-Module";1;"ComputeModule5-CM5";;;

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These files have been created in version 8 of KiCAD.
Some of the 3d models need to be downloaded form the following places and put into the CM5IO.3shapes directory some models are approximations.
https://datasheets.raspberrypi.org/cm5/CM5-step.zip
https://www.molex.com/molex/products/part-detail/memory_card_socket/5033981892
The models provided in the 3dmodels directory are from various manufacturers including Diodes, Hirose, MTCONN, Toby, TRXCOM. Terms and conditions for the use of the models remain with the original manufacture.

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(fp_lib_table
(version 7)
(lib (name "CM5IO")(type "KiCad")(uri "${KIPRJMOD}/CM5IO.pretty")(options "")(descr ""))
)

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(sym_lib_table
(version 7)
(lib (name "CM5IO")(type "KiCad")(uri "${KIPRJMOD}/CM5IO.kicad_sym")(options "")(descr ""))
)