13 KiB
CM5 Carrier Board — Design Document
Purpose: Lean, deployable PTP/instrumentation compute node built on the Raspberry Pi Compute Module 5. Wired gigabit, on-board Wi-Fi via M.2 E-key, 15 V supply input, and the timing/boot/power signals of the official CM5IO J2 header broken out.
Status: Spec frozen (rev A scope). Ready for schematic capture.
Target applications driving the design: (1) external GPS-PPS disciplining an on-board PTP grandmaster; (2) UWB (Arduino prototype) wireless time-sync R&D referenced against GPS truth; (3) MT7915-based transparent Wi-Fi bridge. All three lean on a clean, distributable PPS timing path — hardened in this rev.
Named Wi-Fi target: AsiaRF AW7915 (MediaTek MT7915, mt76 driver) — chosen for mac80211 AP / 4-address(WDS) support needed by the transparent bridge. Being proven out on the bench separately.
1. Design intent
A purpose-built carrier that strips the official CM5IO down to essentials and re-targets it for a powered-by-15V, time-synchronized node:
- Keep: the CM5's own gigabit PHY, one PCIe lane (→ Wi-Fi), USB, GPIO, RTC, timing.
- Drop: HDMI/MIPI display, on-board NVMe (M-key), microSD, PoE.
- Add: 15 V → 5 V front-end with reverse protection; M.2 E-key for a Wi-Fi card; both spare USB exposed as sockets.
The CM5 module carries its own Gigabit Ethernet PHY (Broadcom BCM54210PE) and the wireless radio option, so no external PHY is needed and the single PCIe Gen2 ×1 lane is free for the E-key Wi-Fi card.
2. Feature list (frozen)
| # | Feature | Implementation |
|---|---|---|
| 1 | 15 VDC input | Jack or 2-pin → ideal-diode reverse-polarity FET + TVS → 15→5 V synchronous buck, 5 A |
| 2 | Gigabit Ethernet | CM5 on-module BCM54210PE → 1:1 RJ45 magjack + ESD. No external PHY. |
| 3 | M.2 E-key (Wi-Fi only) | PCIe ×1 Gen2 + CLKREQ/PERST/RF_KILL + 3.3 V. USB pins not connected. |
| 4 | 2× USB-A | Both from CM5 USB 3.0 ports (5 Gb/s, simultaneous) + per-port ESD |
| 5 | USB-C programming | CM5 USB 2.0 → rpiboot / eMMC flashing |
| 6 | RTC + battery | I²C RTC + CR2032 coin cell |
| 7 | 40-pin GPIO header | Standard Pi HAT pinout, 3.3 V Vref |
| 8 | 14-pin header | Exact CM5IO J2 pinout (see §4) |
| 9 | Debug UART | 3-pin header (GND / TX / RX) |
| 10 | GPS connector | PPS + UART(TX/RX) + 3.3 V + GND. Powers + reads a GPS module. |
| 11 | PPS distribution | GPS PPS → TVS → Schmitt buffer → fan-out: CM5 SYNC + 2 header taps (UWB, spare/scope). Board is always a PPS sink (GPS-sourced). |
| 12 | M.2 E-key target | AsiaRF AW7915 (MT7915). 3.3 V rail sized for it (see §5). |
| — | Omitted | microSD, M.2 M-key/NVMe, MIPI DSI/CSI, HDMI, PoE, PPS source/SMA |
Module requirement: standard eMMC CM5 (not Lite) — no microSD or other boot storage on board.
3. CM5 resource allocation (no contention)
| CM5 resource | Destination |
|---|---|
| BCM54210PE GbE PHY | RJ45 magjack |
| PCIe ×1 Gen2 | M.2 E-key (Wi-Fi) |
| USB 2.0 HS | USB-C (programming) |
| USB 3.0 #1 | USB-A #1 |
| USB 3.0 #2 | USB-A #2 |
| Debug UART | 3-pin header |
| GPIO UART (NMEA) | GPS connector — time-of-day from GPS |
| SYNC (IEEE 1588) in | PPS distribution block ← GPS PPS (buffered) |
| GPIO ×~26 | 40-pin header (+ NMEA UART + select lines) |
Every interface lands on its own dedicated connector. The only resource with a historical conflict (USB 2.0) is cleanly assigned to programming, since Bluetooth was dropped (Wi-Fi-only E-key).
4. 14-pin header — CM5IO J2 reference pinout
| Pin | Function | Notes |
|---|---|---|
| 1–2 | nRPIBOOT | Jumper → boot from USB (recovery/flash) |
| 3–4 | EEPROM_nWP | Write-protect CM5 EEPROM |
| 6 | SYNC_OUT | IEEE 1588 timing; bidirectional, 3.3 V (CM5 connector pin 18). Header pinout matches reference; the net is driven by the buffered PPS block (§5a). |
| 12 | PMIC_ENABLE | PMIC power control |
| 13–14 | Wake/shutdown | Push-button wake/shutdown |
Pins 5, 7–11 follow the reference (unassigned / ground). The 14-pin pinout matches CM5IO J2 exactly, but the SYNC net (pin 6 ↔ CM5 connector pin 18) is buffered + ESD-protected at the PPS distribution block (§5a) and is 3.3 V — no level translation needed (verified against refs/CM5IO.kicad_sym; see CM5_Carrier_PinMap.md correction C1).
5. Power architecture
Three regulators, two independent 3.3 V rails — the noisy Wi-Fi RF rail is isolated from the quiet rail that feeds GPS/IO and (critically) the PPS timing circuitry.
J_PWR (15V) ─► D_REV(ideal-diode FET) ─► VIN_PROT ─► [TVS] ─┬─► U_BUCK5 (15→5V, 5A) ─► +5V ─┬─► CM5 +5V
│ └─► USB VBUS sw ─► USB-A ×2
├─► U_BUCK33R (15→3.3V, 4A) ─► +3V3_RF ─► E-key (AW7915)
└─► U_BUCK33A (15→3.3V, 1A) ─► +3V3_AUX ─┬─► GPS module
├─► PPS Schmitt buffer (3V3, no translator)
├─► IO pull-ups / Vref side
└─► RTC domain
Why two 3.3 V rails (not cascade):
- The AW7915 pulls 3–3.5 A at 3.3 V (~11.5 W) in bursty TX patterns. Putting that on its own direct 15→3.3 buck keeps the radio's switching/transient current off the 5 V/compute rail and off the quiet 3.3 V that feeds timing.
- +3V3_AUX is small (~1 A) and quiet — it powers the GPS module, the PPS Schmitt buffer, IO, and RTC. Isolating it from the RF rail protects PPS edge integrity (consistent with the hardened SYNC path).
- +5V buck now only carries CM5 + USB VBUS (not the reflected 3.3 V load), so it stays a clean 5 A part with a smaller inductor.
| Rail | Regulator | Vin | Current | Load |
|---|---|---|---|---|
| +5V | U_BUCK5 | 15 V | ≥5 A | CM5, USB VBUS, fan |
| +3V3_RF | U_BUCK33R | 15 V | 4 A | AW7915 (3–3.5 A) — direct, noise-isolated |
| +3V3_AUX | U_BUCK33A | 15 V | ~1 A | GPS, PPS buffer, IO, RTC — quiet rail |
| +VRTC | CR2032 / ORing | — | µA | CM5 RTC backup |
Buck Vin rating: all three bucks see 15 V nominal → spec parts rated ≥20 V (covers 15 V + load-dump/transient margin). Note the 15→3.3 stages run ~22% duty — pick controllers comfortable with low duty cycle / high Vin (not 6 V-max commodity 5 V-input parts).
- Reverse-polarity + reverse-current: ideal-diode controller / ORing FET at the inlet (low drop vs a passive bridge — important at 15 V).
- Bulk + inrush: input bulk cap with soft-start; consider a hot-swap/inrush limiter if the 15 V source is shared or hot-plugged.
5a. PPS / timing distribution (hardened)
Board is always a PPS sink — GPS is the only source. Single clean input path, fanned out:
GPS PPS ─► [TVS/ESD] ─► [Schmitt buffer] ─┬─► CM5 SYNC (J2 pin-6 net, IEEE 1588 in)
├─► header tap 1 (UWB node)
└─► header tap 2 (spare / scope trigger)
- GPS connector: PPS, UART TX, UART RX, 3.3 V, GND (powers + reads the module). NMEA time-of-day comes in on a 40-pin GPIO UART; PPS provides the precise edge.
- Conditioning: TVS + Schmitt (LVC1G17-class) — protects the CM5 pin and squares the edge for timestamp accuracy. (LVDS/comparator path noted as future if sub-ns distribution skew is ever needed.)
- Fan-out: low-skew buffer to CM5 + 2 header taps; keep tap stubs short and length-similar so the edge arrives coherently.
- 14-pin J2 stays exact — SYNC still appears on J2 pin 6 per reference, but the driven PPS net originates from the buffered distribution block, not a raw off-board stub.
6. Layer stack & routing notes
- 4-layer minimum. Controlled-impedance required for: PCIe ×1 (to E-key) and the 4 GbE MDI pairs (to magjack). 2-layer is not viable.
- Suggested stack: Sig / GND / PWR / Sig. Reference high-speed pairs to a solid plane.
- PCIe: CM5 has on-board AC-coupling on TX; RX coupling caps live on the card side (standard M.2). Length-match the pair; keep PERST/CLKREQ/REFCLK clean.
- GbE: 1:1 magjack, Bob-Smith termination, chassis-gap under the magjack; ESD array on the cable side.
- USB3: length-match SS pairs; ESD (USBLC6-class) on both A-ports.
- DF40 placement: copy the connector placement + keep-outs from the CM5IO KiCad files verbatim to de-risk the high-density interface.
7. BOM skeleton (per board)
| Block | Candidate parts | ~$/bd |
|---|---|---|
| CM5 interface | 2× DF40C-100DS-0.4V (or matched) | 12–18 |
| Power inlet | ideal-diode ctrl (e.g. LM74700 / LTC4359-class) + TVS + FET | 1.5–3 |
| 15→5 V buck | sync buck 5 A (e.g. TPS5450/TPS56x-class) + L + caps | 2–4 |
| 3.3 V rail | sync buck 4 A (for AW7915) + L + caps | 2–4 |
| Ethernet | 1:1 GbE magjack + ESD array | 2–4 |
| M.2 E-key | E-key connector + standoff | 1.5–2 |
| PPS/GPS | Schmitt buffer + TVS + GPS conn (5-pin) + 2 tap headers | 1.5–3 |
| USB | 2× USB-A + 1× USB-C + 3× ESD arrays | 2–3.5 |
| RTC | I²C RTC + CR2032 holder + cell | 1–2 |
| Headers | 40-pin + 14-pin + 3-pin UART | 1–2 |
| Passives / misc | R/C/L, jumpers, LEDs, test points | 2–4 |
| Per-board total | ~28–47 |
DF40 connectors dominate (~50–65 % of BOM). Everything else is commodity.
8. Cost estimate (turnkey PCBA, JLCPCB/PCBWay-class)
| Bucket | Qty 2 (build 5, use 2) | Qty 10 |
|---|---|---|
| 4-layer ENIG fab | $30–60 | $40–85 |
| BOM | $90–145 | $185–290 |
| PCBA setup + placement | $55–95 | $85–150 |
| Total | ~$180–300 | ~$310–525 |
| Per usable board | ~$90–150 (of 2) | $31–53 |
Notes:
- Qty 2 is the worst unit price (all NRE, no volume break). Building 5 and keeping 3 spares is the smart prototype move — bring-up spares are cheap insurance.
- Qty 25–50 drops per-board 30–50 % as NRE amortizes and parts hit price breaks.
- DF40 connectors and the magjack are the items most likely to be consigned/special-order at a fab — check stock early.
- Budget for a second spin: mixed-signal (PCIe + power) rev-A boards rarely ship perfect.
9. Design → fab process
Phase 0 — Setup
- Pull the official CM5 design files (KiCad) from Raspberry Pi (CM5IO is open hardware) — start point for connector placement, power, Ethernet.
- Confirm CM5 variant on the order line: eMMC, wireless optional (you may order non-wireless since the E-key card is your Wi-Fi).
- Pick the Wi-Fi card (e.g. AX210-class E-key) and verify driver support in your target distro/kernel.
Phase 1 — Schematic capture
- Import CM5IO sheets; delete HDMI, MIPI, M-key, microSD, PoE blocks.
- Replace Type-C-power front-end with the 15 V inlet → ideal-diode → 5 A buck block.
- Add M.2 E-key (PCIe + sidebands, USB pins NC), 2× USB-A on USB3, 3.3 V rail.
- Keep RTC, 40-pin, J2 14-pin (exact), debug UART.
- ERC clean.
Phase 2 — Layout
- Place DF40 connectors per reference; lock keep-outs and mounting holes.
- Define 4-layer stack + impedance targets (PCIe ~85–90 Ω diff, USB3 ~90 Ω, Ethernet ~100 Ω).
- Route high-speed first (PCIe, GbE, USB3), then power, then GPIO/headers.
- DRC + impedance check; back-check against CM5 datasheet track-length guidance.
Phase 3 — Prototype fab (build 5, use 2)
- 4-layer, ENIG, turnkey PCBA. Confirm part availability before order (DF40, magjack).
- Lead time ~1–2 weeks fab+assembly typical.
Phase 4 — Bring-up
- Power-rail checkout (no module): verify 5 V/3.3 V, reverse-polarity behavior, inrush.
- Insert CM5; confirm boot, rpiboot via USB-C, eMMC flash.
- Verify GbE link + (if needed) 1588/SYNC on J2 pin 6.
- Enumerate E-key Wi-Fi over PCIe; confirm driver loads.
- USB-A ports: link + storage throughput (~400–450 MB/s expected on USB3 Gen1).
- RTC hold-over test.
Phase 5 — Rev B + production
- Fold bring-up fixes (expect at least one spin).
- SYNC buffering resolved (Schmitt + series R, 3.3 V) — verify PPS edge/jitter at bring-up.
- Scale to qty 25–50 for unit-cost drop.
10. Open / future decisions (parked)
- SYNC buffering: RESOLVED — buffered (Schmitt + TVS), GPS-sourced sink, 2 fan-out taps. See §5a.
- Wi-Fi card: AW7915 (MT7915) named target; bench-validation in progress (4-addr/AP/bridge modes, real 3.3 V draw). Confirm mt76 mode support before committing rev A.
- 3.3 V buck: sized 4 A for AW7915; confirm against the specific AW7915 variant (2T2R 3 A vs 4T4R 3.5 A) once bench numbers are in.
- Storage: none on board; USB-A sockets + external SSD (~450 MB/s, same as native lane ceiling).
- 15 V inlet connector: barrel jack vs locking 2-pin — pick at layout.
- UWB sync (function 2): no rev-A PCB change — Arduino+UWB couples via USB / 40-pin GPIO; references the PPS header tap. Revisit only if a dedicated UWB interface is wanted later.
- PPS distribution skew: Schmitt is fine for 1PPS; LVDS/comparator path is the upgrade if sub-ns inter-node skew ever matters.
- Enclosure / mounting: not yet specified.