c469238dd5
First stage of the power tree. New carrier/Power.kicad_sch (generated by tools/build_power.py): J_PWR 15V inlet -> D_REV LM74700-Q1 ideal-diode controller + Q_REV N-FET (reverse-polarity / reverse-current) -> VIN_PROT, with SMBJ18A input TVS and 100uF/25V || 10uF/50V bulk + VCAP cap. Part-selection note: the spec's buck candidates miss its own >=20V Vin rule (TPS54424=17V, TPS54560=async); the 3 sync bucks (stages 2-4) will use >=30V synchronous parts, datasheet-verified, feeding +5V/+3V3_RF/+3V3_AUX. tools/build_power.py generalizes the build_ekey approach: generic place() attaches a net label / GND symbol per pin (by-name connectivity, grid-snapped); PWR_FLAGs co-located on real pin coords. Verify: ERC 133->133 (zero new); analyzer +16 added, 0 regressions; netlist confirms the ideal-diode topology (+15V_IN/VIN_PROT/GATE_REV/VCAP_REV/GND). Confirm vs LM74700-Q1 datasheet: C_VCAP value, EN tie, FET Vds/SOA, gate R. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
