13 KiB
CM5 Carrier — Pinouts, Nets & BOM
Companion to CM5_Carrier_Design.md. This is the schematic-capture worksheet: connector pinouts, the net list grouped by interface, and a BOM with candidate MPNs.
Sourcing note on CM5 ball/pin numbers: the two 100-pin connectors (J1 = pins 1–100 top, J2mod = pins 101–200 bottom) carry every CM5 signal. Rather than transcribe 200 pins (error-prone), this sheet references CM5 signals by their datasheet net names; pull exact pin numbers from the official CM5 KiCad symbol when capturing. All user-facing connector pinouts (40-pin, 14-pin J2, USB, GPS, PPS, UART) are given exactly. The 40-pin map below is verified against the CM5/Pi-5 standard.
1. Connector inventory & reference designators
| RefDes | Connector | Notes |
|---|---|---|
| J1 / J2MOD | 2× 100-pin DF40 (to CM5) | Hirose DF40C-100DS-0.4V mate; 1.5/2.0/4.0 mm stack options |
| J_PWR | 15 VDC input | barrel jack or 2-pin locking |
| J_ETH | RJ45 magjack (GbE) | 1:1, integrated magnetics |
| J_E | M.2 E-key socket (2230) | Wi-Fi (AW7915) |
| J_USB1 | USB-A (USB3) | |
| J_USB2 | USB-A (USB3) | |
| J_UPROG | USB-C | rpiboot/programming |
| J_GPIO | 40-pin 2.54 mm header | Pi HAT |
| J2 | 14-pin 2.54 mm header | CM5IO J2 reference |
| J_UART | 3-pin header | debug UART |
| J_GPS | 5-pin header | PPS+UART+3V3+GND |
| J_PPS1 | 2-pin header | PPS tap → UWB |
| J_PPS2 | 2-pin header | PPS tap → scope/spare |
| BT1 | CR2032 holder | RTC backup |
| J_FAN | 4-pin JST-SH | PWM fan (optional, keep from ref) |
2. 40-pin GPIO header (J_GPIO) — exact pinout
Standard Raspberry Pi / CM5 HAT pinout. BCM GPIO numbering.
| Pin | Signal | Pin | Signal | |
|---|---|---|---|---|
| 1 | 3V3 | 2 | 5V | |
| 3 | GPIO2 (SDA1) | 4 | 5V | |
| 5 | GPIO3 (SCL1) | 6 | GND | |
| 7 | GPIO4 (GPCLK0) | 8 | GPIO14 (TXD0) | |
| 9 | GND | 10 | GPIO15 (RXD0) | |
| 11 | GPIO17 | 12 | GPIO18 (PCM_CLK) | |
| 13 | GPIO27 | 14 | GND | |
| 15 | GPIO22 | 16 | GPIO23 | |
| 17 | 3V3 | 18 | GPIO24 | |
| 19 | GPIO10 (MOSI) | 20 | GND | |
| 21 | GPIO9 (MISO) | 22 | GPIO25 | |
| 23 | GPIO11 (SCLK) | 24 | GPIO8 (CE0) | |
| 25 | GND | 26 | GPIO7 (CE1) | |
| 27 | GPIO0 (ID_SD) | 28 | GPIO1 (ID_SC) | |
| 29 | GPIO5 | 30 | GND | |
| 31 | GPIO6 | 32 | GPIO12 (PWM0) | |
| 33 | GPIO13 (PWM1) | 34 | GND | |
| 35 | GPIO19 (PCM_FS) | 36 | GPIO16 | |
| 37 | GPIO26 | 38 | GPIO20 (PCM_DIN) | |
| 39 | GND | 40 | GPIO21 (PCM_DOUT) |
NMEA UART assignment (CORRECTED): use UART2 on GPIO4 (pin 7) / GPIO5 (pin 29) → cross to GPS RX/TX on J_GPS, enabled via dtoverlay=uart2. The debug console keeps UART0 (GPIO14/15, pins 8/10) — there are no dedicated debug-UART pins on the CM5 connector (correction C2). Pins 7/29 are committed to GPS when J_GPS is fitted.
Vref: Pin 1/17 3V3 sets HAT logic level. CM5 GPIO bank is 3.3 V by default (R5 fitted equivalent); do not feed 1.8 V unless a deliberate Vref change is made on the module side.
3. 14-pin header (J2) — exact CM5IO reference
| Pin | Net | Function |
|---|---|---|
| 1 | nRPIBOOT | jumper 1–2 → boot from USB |
| 2 | GND | |
| 3 | EEPROM_nWP | jumper 3–4 → write-protect EEPROM |
| 4 | GND | |
| 5 | NC | (reference: unassigned) |
| 6 | SYNC | IEEE 1588 timing — driven by PPS dist block (input to CM5). Maps to CM5 pin 18 Ethernet_SYNC_OUT, 3.3 V. |
| 7 | NC | |
| 8 | NC | |
| 9 | NC | |
| 10 | NC | |
| 11 | NC | |
| 12 | PMIC_ENABLE | power enable/disable |
| 13 | BUTTON (wake/shutdown) | push-button |
| 14 | GND | button return |
CORRECTED (per
refs/CM5IO.kicad_sym): the CM5 timing pin is a singleEthernet_SYNC_OUTon connector pin 18, at 3.3 V, bidirectional (configurable as input). There is no separate 1.8 V SYNC_IN. No level translation is needed — the 3.3 V GPS PPS drives it directly through the Schmitt + a series R. SeeCM5_Carrier_PinMap.md§5 and correction C1.
4. M.2 E-key (J_E) — net assignment (Wi-Fi only, AW7915)
A+E key edge. Populate PCIe + control; leave USB pins NC.
| M.2 pin(s) | Net | To |
|---|---|---|
| 32, 34 (PERST0#, etc.) | PCIE_PERST# | CM5 PCIe PERST |
| CLKREQ0# | PCIE_CLKREQ# | CM5 PCIe CLKREQ |
| REFCLK+ / REFCLK− | PCIE_REFCLK_P/N | CM5 PCIe refclk (100 MHz) |
| PETp0/PETn0 | PCIE_TX_P/N | CM5 PCIe TX (AC-coupled on CM5) |
| PERp0/PERn0 | PCIE_RX_P/N | CM5 PCIe RX (AC-couple caps on carrier) |
| W_DISABLE1# (RF_KILL) | WIFI_DISABLE# | pull-up + optional GPIO |
| 3.3 V pins | +3V3_RF | from 15→3.3 V 4 A RF buck (direct) |
| GND | GND | |
| USB D+/D− (E-key) | NC | Bluetooth not used |
PCIe pair impedance ~85 Ω diff. Keep REFCLK as a matched pair; series-couple per M.2 spec.
5. USB assignments
| Port | CM5 source net | ESD |
|---|---|---|
| J_USB1 (USB-A) | USB3_0 (SS pairs + USB2 D±) | USBLC6-2SC6 |
| J_USB2 (USB-A) | USB3_1 (SS pairs + USB2 D±) | USBLC6-2SC6 |
| J_UPROG (USB-C) | USB2_0 (D±) + CC1/CC2 5.1k | USBLC6-2SC6 |
- USB-C is device/programming (rpiboot): wire D± to CM5 USB 2.0 port; CC1/CC2 each get 5.1 kΩ to GND (sink/UFP). Pair with nRPIBOOT jumper on J2.
- USB-A SuperSpeed pairs ~90 Ω diff; USB2 D± ~90 Ω diff.
- VBUS to USB-A from 5 V via current-limit switch (~0.9–1.2 A/port).
6. PPS / timing distribution — nets
J_GPS.PPS (3V3) ─► [TVS] ─► [Schmitt LVC1G17, 3V3] ─► PPS_CLEAN(3V3) ─┬─► [Rs 33–100Ω] ─► CM5 pin 18 (SYNC, 3V3, cfg input)
├─► J_PPS1 (UWB tap, 3V3)
└─► J_PPS2 (scope tap, 3V3)
| Net | From | To | Level |
|---|---|---|---|
| GPS_PPS_RAW | J_GPS.1 | TVS → Schmitt in | 3.3 V |
| PPS_CLEAN | Schmitt out | fan-out (3 loads) | 3.3 V |
| PPS_SYNC | via Rs | CM5 pin 18 (SYNC) | 3.3 V |
| NMEA_TX | CM5 GPIO4 (UART2 TX, pin 7) | J_GPS.RX | 3.3 V |
| NMEA_RX | CM5 GPIO5 (UART2 RX, pin 29) | J_GPS.TX | 3.3 V |
Corrected detail: CM5 SYNC (pin 18) is 3.3 V — no level translation. The Schmitt squares the off-board GPS edge and the series Rs guards against a driver fight (pin 18 is bidirectional; board always configures it as input). PPS_CLEAN feeds all three loads at 3.3 V. NMEA moved to UART2 (GPIO4/5) so the debug console keeps UART0 (GPIO14/15) — see correction C2 in CM5_Carrier_PinMap.md.
J_GPS (5-pin) pinout
| Pin | Net |
|---|---|
| 1 | PPS (in, 3V3) |
| 2 | NMEA_RX ← GPS TX (CM5 GPIO5 / UART2 RX, pin 29) |
| 3 | NMEA_TX → GPS RX (CM5 GPIO4 / UART2 TX, pin 7) |
| 4 | +3V3_AUX (out, to power module) |
| 5 | GND |
J_PPS1 / J_PPS2 (2-pin each)
| Pin | Net |
|---|---|
| 1 | PPS_CLEAN (3V3) |
| 2 | GND |
7. Power tree — nets
J_PWR (15V) ─► D_REV(ideal-diode FET) ─► VIN_PROT ─► [TVS]
VIN_PROT ─► U_BUCK5 (15→5V, 5A) ─► +5V ─┬─► CM5 +5V (J1 5V input pins)
└─► USB VBUS switch ─► USB-A ×2
VIN_PROT ─► U_BUCK33R (15→3.3V, 4A) ─► +3V3_RF ─► E-key (AW7915) [direct, noise-isolated]
VIN_PROT ─► U_BUCK33A (15→3.3V, 1A) ─► +3V3_AUX ─┬─► GPS module
├─► PPS Schmitt buffer (3V3)
├─► IO pull-ups
└─► RTC domain
| Rail | Source | Current | Load |
|---|---|---|---|
| VIN_PROT | 15 V via ideal-diode | board total | buck inputs |
| +5V | U_BUCK5 | ≥5 A | CM5, USB VBUS, fan |
| +3V3_RF | U_BUCK33R (direct 15→3.3) | 4 A | AW7915 (3–3.5 A) — isolated RF rail |
| +3V3_AUX | U_BUCK33A (direct 15→3.3) | ~1 A | GPS, PPS buffer, IO, RTC — quiet rail |
| +VRTC | CR2032 / +3V3_AUX ORing | µA | CM5 RTC domain |
All three bucks see 15 V → rate ≥20 V. The 15→3.3 stages run ~22% duty; pick low-duty-capable controllers.
CM5 +5 V input lands on the DF40 +5V (input) pins (per 40-pin ref: pins 77/79/81/83 are +5V on the HAT; the module 5 V input is on the DF40 power pins — pull exact pins from KiCad).
8. Ethernet — nets (no external PHY)
CM5 BCM54210PE PHY pins (from DF40) → magjack. Per CM5 datasheet, a 1:1 magjack + ESD is all that's required.
| CM5 net | Magjack | Notes |
|---|---|---|
| ETH_PAIR0_P/N | TX+/− (or MDI0) | 100 Ω diff |
| ETH_PAIR1_P/N | MDI1 | |
| ETH_PAIR2_P/N | MDI2 | |
| ETH_PAIR3_P/N | MDI3 | gigabit uses all 4 |
| ETH_nLED1/2/3 | jack LEDs (3V3) | activity/link |
| Bob-Smith term + ESD | cable side | TVS array, 75 Ω + 1 nF terms |
PoE pins of the magjack: leave unloaded / NC (no PoE in this design).
9. RTC
| Net | Part | Notes |
|---|---|---|
| RTC_SDA/SCL | CM5 I2C (dedicated RTC I2C on CM5) | CM5 has internal RTC; carrier provides battery backup |
| +VRTC | CR2032 via BT1 | back-up to CM5 RTC battery pin |
CM5 has an on-module RTC; the carrier mainly provides the CR2032 backup cell to the CM5 RTC battery input (per CM5IO reference). If an external I²C RTC is also wanted (redundancy), add e.g. PCF85063A on a GPIO I²C — optional, default is just the coin cell to CM5.
10. Bill of Materials (per board) — candidate MPNs
| # | RefDes | Qty | Description | Candidate MPN | ~$ |
|---|---|---|---|---|---|
| 1 | J1,J2MOD | 2 | 100-pin DF40 0.4 mm receptacle | Hirose DF40C-100DS-0.4V(51) | 12–18 |
| 2 | U_BUCK5 | 1 | Sync buck 15→5 V, ≥5 A (≥20 V Vin) | TI TPS54560 / MPS MP2316 | 1.5–3 |
| 3 | U_BUCK33R | 1 | Sync buck 15→3.3 V, 4 A (RF rail, ≥20 V Vin, low-duty) | TI TPS54424 / MPS MP2143 | 1–2 |
| 3b | U_BUCK33A | 1 | Sync buck 15→3.3 V, 1 A (AUX/quiet rail, ≥20 V Vin) | TI TPS54202 / MPS MP2459 | 0.5–1.2 |
| 4 | D_REV | 1 | Ideal-diode/reverse-polarity ctrl + FET | TI LM74700-Q1 + CSD18xx FET | 1.2–2.5 |
| 5 | TVS_IN | 1 | TVS, >15 V standoff (e.g. 18 V) | SMBJ18A | 0.2 |
| 6 | J_ETH | 1 | RJ45 1:1 GbE magjack | Pulse JXD0-0001NL / Bel V890-1AX | 2–4 |
| 7 | ESD_ETH | 1 | Ethernet ESD array | TI TPD4E1U06 / Bourns | 0.3–0.6 |
| 8 | J_E | 1 | M.2 E-key (A+E) 2230 conn + standoff | Amphenol/Attend 119A-92A00 | 1.2–2 |
| 9 | C_PCIE | 4 | PCIe RX AC-couple 0.1 µF | GRM 0402 100 nF | 0.05 |
| 10 | J_USB1/2 | 2 | USB-A USB3.0 right-angle | Amphenol UE27AC54100 | 0.8–1.4 ea |
| 11 | J_UPROG | 1 | USB-C 16-pin (USB2 + CC) | GCT USB4085 | 0.5–1 |
| 12 | ESD_USB | 3 | USB ESD array | ST USBLC6-2SC6 | 0.15 ea |
| 13 | U_VBUS | 1 | USB VBUS current-limit switch | TI TPS2552 / AP22653 | 0.5–1 |
| 14 | U_SCHMITT | 1 | Single Schmitt buffer 3V3 | TI SN74LVC1G17 | 0.1 |
| 15 | 0 | REMOVED — SYNC is 3.3 V, no translation needed (correction C1). Replace with one 0402 series R (in passives). | — | — | |
| 16 | TVS_PPS | 1 | Low-cap TVS on PPS in | ESD9B / PESD | 0.1 |
| 17 | J_GPS | 1 | 5-pin 2.54 header | generic | 0.1 |
| 18 | J_PPS1/2 | 2 | 2-pin 2.54 header | generic | 0.05 ea |
| 19 | J_GPIO | 1 | 40-pin 2.54 dual header | generic | 0.5–0.8 |
| 20 | J2 | 1 | 14-pin 2.54 header | generic | 0.2 |
| 21 | J_UART | 1 | 3-pin 2.54 header | generic | 0.05 |
| 22 | BT1 | 1 | CR2032 holder + cell | Keystone 1058 + cell | 0.4–0.8 |
| 23 | J_PWR | 1 | 15 V barrel jack or 2-pin | CUI PJ-102AH | 0.4–0.8 |
| 24 | J_FAN | 1 | 4-pin JST-SH PWM fan → CM5 FAN_PWM (pin 19) + FAN_TACHO (pin 16) | JST SM04B-SRSS | 0.3 |
| 25 | — | ~60 | Passives (R/C/L), LEDs, TP, jumpers | 0402/0603 | 2–4 |
| Per-board BOM total | ~28–47 |
DF40 pair (line 1) = ~45–60% of BOM. Everything else commodity.
11. Net list summary (by interface)
| Interface | Nets | Endpoints |
|---|---|---|
| Power in | J_PWR, VIN_PROT, +5V, +3V3_RF, +3V3_AUX, +VRTC | J_PWR → D_REV → 3 bucks → CM5/E-key/IO |
| PCIe (E-key) | PCIE_TX_P/N, PCIE_RX_P/N, REFCLK_P/N, PERST#, CLKREQ#, W_DISABLE# | CM5 ↔ J_E |
| Ethernet | ETH_PAIR0-3_P/N, ETH_nLED1-3 | CM5 PHY ↔ J_ETH |
| USB3 #1 | USB3_0 SS±, USB2 D± | CM5 ↔ J_USB1 |
| USB3 #2 | USB3_1 SS±, USB2 D± | CM5 ↔ J_USB2 |
| USB2 prog | USB2_0 D±, CC1/CC2 | CM5 ↔ J_UPROG |
| PPS/timing | GPS_PPS_RAW, PPS_CLEAN, PPS_SYNC_18 | J_GPS → buffer → CM5 SYNC + J_PPS1/2 |
| NMEA UART | NMEA_TX, NMEA_RX | J_GPIO(14/15) ↔ J_GPS |
| Debug UART | DBG_TX, DBG_RX | CM5 debug UART ↔ J_UART |
| GPIO | GPIO0-27 | CM5 ↔ J_GPIO |
| Boot/ctrl | nRPIBOOT, EEPROM_nWP, PMIC_EN, BUTTON | CM5 ↔ J2 |
| RTC | +VRTC, RTC_SDA/SCL | BT1 → CM5 |
12. Schematic-capture checklist
- Import CM5 KiCad symbol from
refs/CM5IO.kicad_sym— pin map is now resolved inCM5_Carrier_PinMap.md(all 200 pins). - SYNC (pin 18) is 3.3 V — drive directly from the Schmitt via a series R; no level translator (corrected).
- AC-couple PCIe RX on carrier (TX coupled on CM5).
- CC 5.1 kΩ pulldowns on USB-C; nRPIBOOT jumper logic.
- Magjack PoE pins NC; Bob-Smith + ESD on cable side.
- Both 15→3.3 buck inductors/thermals sized for their rails (RF 4 A, AUX 1 A); all bucks rated ≥20 V Vin, low-duty-capable.
- VBUS current-limit per USB-A port.
- Confirm CM5 5 V input pin group and decoupling per datasheet.