Power sheet stage 1: 15V input protection (ideal-diode + TVS)
First stage of the power tree. New carrier/Power.kicad_sch (generated by tools/build_power.py): J_PWR 15V inlet -> D_REV LM74700-Q1 ideal-diode controller + Q_REV N-FET (reverse-polarity / reverse-current) -> VIN_PROT, with SMBJ18A input TVS and 100uF/25V || 10uF/50V bulk + VCAP cap. Part-selection note: the spec's buck candidates miss its own >=20V Vin rule (TPS54424=17V, TPS54560=async); the 3 sync bucks (stages 2-4) will use >=30V synchronous parts, datasheet-verified, feeding +5V/+3V3_RF/+3V3_AUX. tools/build_power.py generalizes the build_ekey approach: generic place() attaches a net label / GND symbol per pin (by-name connectivity, grid-snapped); PWR_FLAGs co-located on real pin coords. Verify: ERC 133->133 (zero new); analyzer +16 added, 0 regressions; netlist confirms the ideal-diode topology (+15V_IN/VIN_PROT/GATE_REV/VCAP_REV/GND). Confirm vs LM74700-Q1 datasheet: C_VCAP value, EN tie, FET Vds/SOA, gate R. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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@@ -837,6 +837,10 @@
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[
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"Power"
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"text_variables": {}
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@@ -3469,6 +3469,16 @@
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(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55" (page "4"))))
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)
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(at 205 60)
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(size 30 20)
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(fill (color 255 255 255 0.0000))
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(uuid "9c7ccf72-dd3e-5ed3-bb43-2939833eb069")
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(property "Sheetname" "Power" (at 205 56.18 0) (effects (font (size 1.27 1.27)) (justify left bottom)))
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(property "Sheetfile" "Power.kicad_sch" (at 205 57.45 0) (effects (font (size 1.27 1.27)) (justify left top)))
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(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55" (page "5"))))
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)
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(sheet_instances
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(page "1")
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1803
carrier/Power.kicad_sch
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1803
carrier/Power.kicad_sch
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