many eda additions

analysis/baseline/cm5io_sim.json

@@ -0,0 +1,220 @@
+{
+  "analyzer_type": "spice",
+  "schema_version": "1.3.0",
+  "summary": {
+    "total": 8,
+    "total_findings": 0,
+    "pass": 8,
+    "warn": 0,
+    "fail": 0,
+    "skip": 0,
+    "by_severity": {
+      "error": 0,
+      "warning": 0,
+      "info": 8
+    }
+  },
+  "findings": [],
+  "simulation_results": [
+    {
+      "subcircuit_type": "voltage_divider",
+      "components": [
+        "R15",
+        "R16"
+      ],
+      "expected": {
+        "ratio": 0.180328,
+        "vout_V": 0.5950823999999999
+      },
+      "simulated": {
+        "vout_V": 0.595082
+      },
+      "delta": {
+        "vout_error_pct": 0.0
+      },
+      "status": "pass",
+      "elapsed_s": 1.214,
+      "reference": "R15/R16"
+    },
+    {
+      "subcircuit_type": "voltage_divider",
+      "components": [
+        "R15",
+        "R16"
+      ],
+      "expected": {
+        "ratio": 0.180328,
+        "vout_V": 0.5950823999999999
+      },
+      "simulated": {
+        "vout_V": 0.595082
+      },
+      "delta": {
+        "vout_error_pct": 0.0
+      },
+      "status": "pass",
+      "elapsed_s": 0.021,
+      "reference": "R15/R16"
+    },
+    {
+      "subcircuit_type": "decoupling",
+      "components": [
+        "C18",
+        "C9",
+        "C12",
+        "C6",
+        "C4"
+      ],
+      "rail": "/00000000-0000-0000-0000-00005ed4bb5b/+5v",
+      "cap_count": 6,
+      "expected": {},
+      "simulated": {
+        "z_min_ohms": 0.0078,
+        "z_at_1MHz_ohms": 0.0093,
+        "z_at_100kHz_ohms": 0.0781
+      },
+      "delta": {},
+      "model_note": "generic ESR + parasitic L from self-resonant frequency",
+      "status": "pass",
+      "note": "Z=0.009\u03a9 at 1MHz",
+      "elapsed_s": 0.016,
+      "reference": "C18/C9/C12/C6/C4"
+    },
+    {
+      "subcircuit_type": "decoupling",
+      "components": [
+        "C2"
+      ],
+      "rail": "+5v",
+      "cap_count": 1,
+      "expected": {},
+      "simulated": {
+        "z_min_ohms": 0.0158,
+        "f_at_zmin_hz": 1678740.0,
+        "z_at_1MHz_ohms": 0.0188,
+        "z_at_100kHz_ohms": 0.1594
+      },
+      "delta": {},
+      "model_note": "generic ESR + parasitic L from self-resonant frequency",
+      "status": "pass",
+      "note": "Z=0.019\u03a9 at 1MHz",
+      "elapsed_s": 0.013,
+      "reference": "C2"
+    },
+    {
+      "subcircuit_type": "decoupling",
+      "components": [
+        "C7",
+        "C3",
+        "C8"
+      ],
+      "rail": "VBUS",
+      "cap_count": 3,
+      "expected": {},
+      "simulated": {
+        "z_min_ohms": 0.0075,
+        "z_at_1MHz_ohms": 0.009,
+        "z_at_100kHz_ohms": 0.0569
+      },
+      "delta": {},
+      "model_note": "generic ESR + parasitic L from self-resonant frequency",
+      "status": "pass",
+      "note": "Z=0.009\u03a9 at 1MHz",
+      "elapsed_s": 0.013,
+      "reference": "C7/C3/C8"
+    },
+    {
+      "subcircuit_type": "regulator_feedback",
+      "components": [
+        "R15",
+        "R16"
+      ],
+      "regulator": "U8",
+      "expected": {
+        "ratio": 0.180328,
+        "vref_V": 0.6,
+        "vfb_V": 0.599951256,
+        "vin_V": 3.327
+      },
+      "simulated": {
+        "vfb_V": 0.6
+      },
+      "delta": {
+        "vfb_error_pct": 0.0
+      },
+      "status": "pass",
+      "elapsed_s": 0.01,
+      "reference": "R15/R16"
+    },
+    {
+      "subcircuit_type": "inrush",
+      "components": [
+        "C7",
+        "C3",
+        "C8"
+      ],
+      "regulator": "U6",
+      "expected": {
+        "v_target_V": 5.0,
+        "estimated_inrush_A": 1.2
+      },
+      "simulated": {
+        "v_settled_V": 5.0
+      },
+      "delta": {
+        "v_settle_error_pct": 0.0
+      },
+      "status": "pass",
+      "note": "Transient simulated",
+      "elapsed_s": 0.013,
+      "reference": "C7/C3/C8"
+    },
+    {
+      "subcircuit_type": "inrush",
+      "components": [
+        "C16",
+        "C19",
+        "C14",
+        "C15",
+        "C17"
+      ],
+      "regulator": "U8",
+      "expected": {
+        "v_target_V": 3.327,
+        "estimated_inrush_A": 0.133
+      },
+      "simulated": {
+        "v_settled_V": 3.327
+      },
+      "delta": {
+        "v_settle_error_pct": 0.0
+      },
+      "status": "pass",
+      "note": "Transient simulated",
+      "elapsed_s": 0.011,
+      "reference": "C16/C19/C14/C15/C17"
+    }
+  ],
+  "trust_summary": {
+    "total_findings": 0,
+    "trust_level": "high",
+    "by_confidence": {
+      "deterministic": 0,
+      "heuristic": 0,
+      "datasheet-backed": 0
+    },
+    "by_evidence_source": {
+      "datasheet": 0,
+      "topology": 0,
+      "heuristic_rule": 0,
+      "symbol_footprint": 0,
+      "bom": 0,
+      "geometry": 0,
+      "api_lookup": 0
+    },
+    "provenance_coverage_pct": null
+  },
+  "total_elapsed_s": 1.31,
+  "simulator": "/opt/homebrew/bin/ngspice",
+  "ngspice": "/opt/homebrew/bin/ngspice"
+}

analysis/spice_runs/decoupling_C18_C9_C12_C6_C4.cir

@@ -0,0 +1,38 @@
+* Auto-generated testbench for decoupling analysis: /00000000-0000-0000-0000-00005ed4bb5b/+5v rail
+* 6 capacitor(s) in parallel, series R-L-C model
+* Model: ESR/ESL from pdn_impedance (package-based)
+
+R_esr_C18 rail n_esr_0 948.7m
+L_par_C18 n_esr_0 n_lpar_0 500p
+C18 n_lpar_0 0 100n
+R_esr_C9 rail n_esr_1 948.7m
+L_par_C9 n_esr_1 n_lpar_1 500p
+C9 n_lpar_1 0 100n
+R_esr_C12 rail n_esr_2 948.7m
+L_par_C12 n_esr_2 n_lpar_2 500p
+C12 n_lpar_2 0 100n
+R_esr_C6 rail n_esr_3 15.8m
+L_par_C6 n_esr_3 n_lpar_3 900p
+C6 n_lpar_3 0 10u
+R_esr_C4 rail n_esr_4 15.8m
+L_par_C4 n_esr_4 n_lpar_4 900p
+C4 n_lpar_4 0 10u
+R_esr_C10 rail n_esr_5 948.7m
+L_par_C10 n_esr_5 n_lpar_5 500p
+C10 n_lpar_5 0 100n
+
+* 1A AC current source into the rail node — V(rail) = Z(f)
+IAC 0 rail DC 0 AC 1
+
+.control
+ac dec 200 100 100Meg
+let z_mag = vm(rail)
+meas ac z_min min z_mag
+meas ac f_at_zmin when z_mag=z_min
+meas ac z_at_1M find vm(rail) at=1Meg
+meas ac z_at_100k find vm(rail) at=100k
+echo "z_min=$&z_min f_at_zmin=$&f_at_zmin z_at_1M=$&z_at_1M z_at_100k=$&z_at_100k n_caps=6" > analysis/spice_runs/decoupling_C18_C9_C12_C6_C4.out
+quit
+.endc
+
+.end

analysis/spice_runs/decoupling_C18_C9_C12_C6_C4.log

@@ -0,0 +1,24 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for decoupling analysis: /00000000-0000-0000-0000-00005ed4bb5b/+5v rail
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+No. of Data Rows : 1201
+z_min               =  7.76885e-03 at=  1.67880e+06
+ meas ac f_at_zmin when z_mag=7.768850e-03 failed!
+
+z_at_1m             =  9.25020e-03
+z_at_100k           =  7.81266e-02
+ngspice-46 done
+
+=== stderr ===
+
+Error: measure  f_at_zmin  when(WHEN) : out of interval
+Error: &f_at_zmin: no such variable.
+

analysis/spice_runs/decoupling_C18_C9_C12_C6_C4.out

@@ -0,0 +1 @@
+z_min=0.00776885 f_at_zmin= z_at_1M=0.0092502 z_at_100k=0.0781266 n_caps=6

analysis/spice_runs/decoupling_C2.cir

@@ -0,0 +1,23 @@
+* Auto-generated testbench for decoupling analysis: +5v rail
+* 1 capacitor(s) in parallel, series R-L-C model
+* Model: ESR/ESL from pdn_impedance (package-based)
+
+R_esr_C2 rail n_esr_0 15.8m
+L_par_C2 n_esr_0 n_lpar_0 900p
+C2 n_lpar_0 0 10u
+
+* 1A AC current source into the rail node — V(rail) = Z(f)
+IAC 0 rail DC 0 AC 1
+
+.control
+ac dec 200 100 100Meg
+let z_mag = vm(rail)
+meas ac z_min min z_mag
+meas ac f_at_zmin when z_mag=z_min
+meas ac z_at_1M find vm(rail) at=1Meg
+meas ac z_at_100k find vm(rail) at=100k
+echo "z_min=$&z_min f_at_zmin=$&f_at_zmin z_at_1M=$&z_at_1M z_at_100k=$&z_at_100k n_caps=1" > analysis/spice_runs/decoupling_C2.out
+quit
+.endc
+
+.end

analysis/spice_runs/decoupling_C2.log

@@ -0,0 +1,40 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for decoupling analysis: +5v rail
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+No. of Data Rows : 1201
+z_min               =  1.58000e-02 at=  1.67880e+06
+f_at_zmin           =  1.67874e+06
+z_at_1m             =  1.88393e-02
+z_at_100k           =  1.59375e-01
+ngspice-46 done
+
+=== stderr ===
+Warning: singular matrix:  check node n_lpar_0
+
+Note: Starting dynamic gmin stepping
+Warning: singular matrix:  check node n_lpar_0
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Warning: singular matrix:  check node n_lpar_0
+
+Warning: singular matrix:  check node n_lpar_0
+
+Warning: singular matrix:  check node n_lpar_0
+
+Warning: singular matrix:  check node n_lpar_0
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+

analysis/spice_runs/decoupling_C2.out

@@ -0,0 +1 @@
+z_min=0.0158 f_at_zmin=1.67874E+06 z_at_1M=0.0188393 z_at_100k=0.159375 n_caps=1

analysis/spice_runs/decoupling_C7_C3_C8.cir

@@ -0,0 +1,29 @@
+* Auto-generated testbench for decoupling analysis: VBUS rail
+* 3 capacitor(s) in parallel, series R-L-C model
+* Model: ESR/ESL from pdn_impedance (package-based)
+
+R_esr_C7 rail n_esr_0 15.8m
+L_par_C7 n_esr_0 n_lpar_0 900p
+C7 n_lpar_0 0 10u
+R_esr_C3 rail n_esr_1 100m
+L_par_C3 n_esr_1 n_lpar_1 7.5n
+C3 n_lpar_1 0 100u
+R_esr_C8 rail n_esr_2 15.8m
+L_par_C8 n_esr_2 n_lpar_2 900p
+C8 n_lpar_2 0 10u
+
+* 1A AC current source into the rail node — V(rail) = Z(f)
+IAC 0 rail DC 0 AC 1
+
+.control
+ac dec 200 100 100Meg
+let z_mag = vm(rail)
+meas ac z_min min z_mag
+meas ac f_at_zmin when z_mag=z_min
+meas ac z_at_1M find vm(rail) at=1Meg
+meas ac z_at_100k find vm(rail) at=100k
+echo "z_min=$&z_min f_at_zmin=$&f_at_zmin z_at_1M=$&z_at_1M z_at_100k=$&z_at_100k n_caps=3" > analysis/spice_runs/decoupling_C7_C3_C8.out
+quit
+.endc
+
+.end

analysis/spice_runs/decoupling_C7_C3_C8.log

@@ -0,0 +1,44 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for decoupling analysis: vbus rail
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+No. of Data Rows : 1201
+z_min               =  7.52546e-03 at=  1.67880e+06
+ meas ac f_at_zmin when z_mag=7.525463e-03 failed!
+
+z_at_1m             =  8.98325e-03
+z_at_100k           =  5.69392e-02
+ngspice-46 done
+
+=== stderr ===
+Warning: singular matrix:  check node n_lpar_1
+
+Note: Starting dynamic gmin stepping
+Warning: singular matrix:  check node rail
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Warning: singular matrix:  check node rail
+
+Warning: singular matrix:  check node rail
+
+Warning: singular matrix:  check node rail
+
+Warning: singular matrix:  check node rail
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Error: measure  f_at_zmin  when(WHEN) : out of interval
+Error: &f_at_zmin: no such variable.
+

analysis/spice_runs/decoupling_C7_C3_C8.out

@@ -0,0 +1 @@
+z_min=0.00752546 f_at_zmin= z_at_1M=0.00898326 z_at_100k=0.0569392 n_caps=3

analysis/spice_runs/inrush_idx0.cir

@@ -0,0 +1,25 @@
+* Auto-generated testbench for inrush analysis: U6 (LDO)
+* Output: 5.0V, 120.0µF total capacitance
+* Soft-start: 0.5ms ramp
+
+* Voltage source with linear ramp (soft-start) — 10us delay before ramp
+Vreg ramp 0 PWL(0 0 10u 0 510u 5.0)
+* Regulator output impedance
+Rout ramp out 100m
+
+* Output capacitors
+C7 out 0 10u
+C3 out 0 100u
+C8 out 0 10u
+
+.control
+tran 1u 1.5m
+let i_out = abs(i(Rout))
+let i_peak = vecmax(i_out)
+let t_peak = i_out[vecmin(abs(i_out - i_peak))]
+meas tran v_settled find v(out) at=1.35m
+echo "i_peak=$&i_peak t_peak=$&t_peak v_settled=$&v_settled v_target=5.0 r_out=0.1" > analysis/spice_runs/inrush_idx0.out
+quit
+.endc
+
+.end

analysis/spice_runs/inrush_idx0.log

@@ -0,0 +1,37 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for inrush analysis: u6 (ldo)
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+Initial Transient Solution
+--------------------------
+
+Node                                   Voltage
+----                                   -------
+ramp                                         0
+out                                          0
+vreg#branch                                  0
+
+
+No. of Data Rows : 1517
+v_settled           =  5.00000e+00
+ngspice-46 done
+
+=== stderr ===
+
+Error: no such function as i,
+    or i(rout) is not available.
+Error: RHS "abs(i(rout))" invalid
+Warning from checkvalid: vector i_out is not available or has zero length.
+Error: RHS "vecmax(i_out)" invalid
+Warning from checkvalid: vector i_out is not available or has zero length.
+Error: RHS "i_out[vecmin(abs(i_out - i_peak))]" invalid
+Error: &i_peak: no such variable.
+Error: &t_peak: no such variable.
+

analysis/spice_runs/inrush_idx0.out

@@ -0,0 +1 @@
+i_peak= t_peak= v_settled=5 v_target=5.0 r_out=0.1

analysis/spice_runs/inrush_idx1.cir

@@ -0,0 +1,27 @@
+* Auto-generated testbench for inrush analysis: U8 (switching)
+* Output: 3.327V, 40.1µF total capacitance
+* Soft-start: 1.0ms ramp
+
+* Voltage source with linear ramp (soft-start) — 10us delay before ramp
+Vreg ramp 0 PWL(0 0 10u 0 1.01m 3.327)
+* Regulator output impedance
+Rout ramp out 10m
+
+* Output capacitors
+C16 out 0 10u
+C19 out 0 100n
+C14 out 0 10u
+C15 out 0 10u
+C17 out 0 10u
+
+.control
+tran 2u 3m
+let i_out = abs(i(Rout))
+let i_peak = vecmax(i_out)
+let t_peak = i_out[vecmin(abs(i_out - i_peak))]
+meas tran v_settled find v(out) at=2.7m
+echo "i_peak=$&i_peak t_peak=$&t_peak v_settled=$&v_settled v_target=3.327 r_out=0.01" > analysis/spice_runs/inrush_idx1.out
+quit
+.endc
+
+.end

analysis/spice_runs/inrush_idx1.log

@@ -0,0 +1,37 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for inrush analysis: u8 (switching)
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+Initial Transient Solution
+--------------------------
+
+Node                                   Voltage
+----                                   -------
+ramp                                         0
+out                                          0
+vreg#branch                                  0
+
+
+No. of Data Rows : 1518
+v_settled           =  3.32700e+00
+ngspice-46 done
+
+=== stderr ===
+
+Error: no such function as i,
+    or i(rout) is not available.
+Error: RHS "abs(i(rout))" invalid
+Warning from checkvalid: vector i_out is not available or has zero length.
+Error: RHS "vecmax(i_out)" invalid
+Warning from checkvalid: vector i_out is not available or has zero length.
+Error: RHS "i_out[vecmin(abs(i_out - i_peak))]" invalid
+Error: &i_peak: no such variable.
+Error: &t_peak: no such variable.
+

analysis/spice_runs/inrush_idx1.out

@@ -0,0 +1 @@
+i_peak= t_peak= v_settled=3.327 v_target=3.327 r_out=0.01

analysis/spice_runs/regulator-feedback_U8_R15_R16.cir

@@ -0,0 +1,20 @@
+* Auto-generated testbench for regulator feedback: U8
+* Divider: R15/R16, ratio=0.1803
+* Expected Vout=3.327V, Vfb=0.6000V (Vref=0.6V)
+* Topology: standard
+* Model: ideal passives (exact for DC divider)
+
+VIN out_rail 0 DC 3.327
+R15 out_rail fb_net 10k
+R16 fb_net 0 2.2k
+
+.control
+op 
+let vfb_sim = v(fb_net)
+let expected = 0.599951256
+let error_pct = abs(vfb_sim - expected) / expected * 100
+echo "vfb_sim=$&vfb_sim error_pct=$&error_pct expected=0.599951256 vin=3.327 vref=0.6" > analysis/spice_runs/regulator-feedback_U8_R15_R16.out
+quit
+.endc
+
+.end

analysis/spice_runs/regulator-feedback_U8_R15_R16.log

@@ -0,0 +1,16 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for regulator feedback: u8
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+No. of Data Rows : 1
+ngspice-46 done
+
+=== stderr ===
+

analysis/spice_runs/regulator-feedback_U8_R15_R16.out

@@ -0,0 +1 @@
+vfb_sim=0.599951 error_pct=7.27272E-05 expected=0.599951256 vin=3.327 vref=0.6

analysis/spice_runs/voltage-divider_R15_R16.cir

@@ -0,0 +1,17 @@
+* Auto-generated testbench for voltage divider: R15/R16
+* Expected Vout = 3.3 * 0.180328 = 0.5951 V
+* Model: ideal passives (exact, unloaded)
+
+VIN M2_3v3 0 DC 3.3
+R15 M2_3v3 FB 10k
+R16 FB 0 2.2k
+
+.control
+op 
+let vout_sim = v(FB)
+let error_pct = abs(vout_sim - 0.5950823999999999) / 0.5950823999999999 * 100
+echo "vout_sim=$&vout_sim error_pct=$&error_pct expected=0.5950823999999999" > analysis/spice_runs/voltage-divider_R15_R16.out
+quit
+.endc
+
+.end

analysis/spice_runs/voltage-divider_R15_R16.log

@@ -0,0 +1,16 @@
+=== stdout ===
+
+Note: No compatibility mode selected!
+
+
+Circuit: * auto-generated testbench for voltage divider: r15/r16
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Using SPARSE 1.3 as Direct Linear Solver
+
+No. of Data Rows : 1
+ngspice-46 done
+
+=== stderr ===
+

analysis/spice_runs/voltage-divider_R15_R16.out

@@ -0,0 +1 @@
+vout_sim=0.595082 error_pct=7.27272E-05 expected=0.5950823999999999