Companion to `CM5_Carrier_Design.md`. This is the schematic-capture worksheet: connector pinouts, the net list grouped by interface, and a BOM with candidate MPNs.
> **Sourcing note on CM5 ball/pin numbers:** the two 100-pin connectors (J1 = pins 1–100 top, J2mod = pins 101–200 bottom) carry every CM5 signal. Rather than transcribe 200 pins (error-prone), this sheet references CM5 signals by their **datasheet net names**; pull exact pin numbers from the official CM5 KiCad symbol when capturing. All *user-facing* connector pinouts (40-pin, 14-pin J2, USB, GPS, PPS, UART) are given exactly. The 40-pin map below is verified against the CM5/Pi-5 standard.
| J_FAN | 4-pin JST-SH | PWM fan (optional, keep from ref) |
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## 2. 40-pin GPIO header (J_GPIO) — exact pinout
Standard Raspberry Pi / CM5 HAT pinout. **BCM GPIO** numbering.
| Pin | Signal | | Pin | Signal |
|-----|--------|--|-----|--------|
| 1 | 3V3 | | 2 | 5V |
| 3 | GPIO2 (SDA1) | | 4 | 5V |
| 5 | GPIO3 (SCL1) | | 6 | GND |
| 7 | GPIO4 (GPCLK0) | | 8 | GPIO14 (TXD0) |
| 9 | GND | | 10 | GPIO15 (RXD0) |
| 11 | GPIO17 | | 12 | GPIO18 (PCM_CLK) |
| 13 | GPIO27 | | 14 | GND |
| 15 | GPIO22 | | 16 | GPIO23 |
| 17 | 3V3 | | 18 | GPIO24 |
| 19 | GPIO10 (MOSI) | | 20 | GND |
| 21 | GPIO9 (MISO) | | 22 | GPIO25 |
| 23 | GPIO11 (SCLK) | | 24 | GPIO8 (CE0) |
| 25 | GND | | 26 | GPIO7 (CE1) |
| 27 | GPIO0 (ID_SD) | | 28 | GPIO1 (ID_SC) |
| 29 | GPIO5 | | 30 | GND |
| 31 | GPIO6 | | 32 | GPIO12 (PWM0) |
| 33 | GPIO13 (PWM1) | | 34 | GND |
| 35 | GPIO19 (PCM_FS) | | 36 | GPIO16 |
| 37 | GPIO26 | | 38 | GPIO20 (PCM_DIN) |
| 39 | GND | | 40 | GPIO21 (PCM_DOUT) |
**NMEA UART assignment (CORRECTED):** use **UART2** on GPIO4 (pin 7) / GPIO5 (pin 29) → cross to GPS RX/TX on J_GPS, enabled via `dtoverlay=uart2`. The **debug console keeps UART0** (GPIO14/15, pins 8/10) — there are no dedicated debug-UART pins on the CM5 connector (correction C2). Pins 7/29 are committed to GPS when J_GPS is fitted.
**Vref:** Pin 1/17 3V3 sets HAT logic level. CM5 GPIO bank is 3.3 V by default (R5 fitted equivalent); do not feed 1.8 V unless a deliberate Vref change is made on the module side.
| 6 | **SYNC** | IEEE 1588 timing — driven by PPS dist block (input to CM5). Maps to CM5 pin 18 `Ethernet_SYNC_OUT`, **3.3 V**. |
| 7 | NC | |
| 8 | NC | |
| 9 | NC | |
| 10 | NC | |
| 11 | NC | |
| 12 | PMIC_ENABLE | power enable/disable |
| 13 | BUTTON (wake/shutdown) | push-button |
| 14 | GND | button return |
> **CORRECTED (per `refs/CM5IO.kicad_sym`):** the CM5 timing pin is a single **`Ethernet_SYNC_OUT` on connector pin 18, at 3.3 V**, bidirectional (configurable as input). There is no separate 1.8 V SYNC_IN. **No level translation is needed** — the 3.3 V GPS PPS drives it directly through the Schmitt + a series R. See `CM5_Carrier_PinMap.md` §5 and correction C1.
**Corrected detail:** CM5 SYNC (pin 18) is **3.3 V** — no level translation. The Schmitt squares the off-board GPS edge and the series Rs guards against a driver fight (pin 18 is bidirectional; board always configures it as input). PPS_CLEAN feeds all three loads at 3.3 V. **NMEA moved to UART2 (GPIO4/5)** so the debug console keeps UART0 (GPIO14/15) — see correction C2 in `CM5_Carrier_PinMap.md`.
All three bucks see 15 V → rate ≥20 V. The 15→3.3 stages run ~22% duty; pick low-duty-capable controllers.
CM5 +5 V input lands on the DF40 **+5V (input)** pins (per 40-pin ref: pins 77/79/81/83 are +5V on the HAT; the module 5 V input is on the DF40 power pins — pull exact pins from KiCad).
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## 8. Ethernet — nets (no external PHY)
CM5 BCM54210PE PHY pins (from DF40) → magjack. Per CM5 datasheet, a 1:1 magjack + ESD is all that's required.
| CM5 net | Magjack | Notes |
|---------|---------|-------|
| ETH_PAIR0_P/N | TX+/− (or MDI0) | 100 Ω diff |
| ETH_PAIR1_P/N | MDI1 | |
| ETH_PAIR2_P/N | MDI2 | |
| ETH_PAIR3_P/N | MDI3 | gigabit uses all 4 |
| ETH_nLED1/2/3 | jack LEDs (3V3) | activity/link |
| Bob-Smith term + ESD | cable side | TVS array, 75 Ω + 1 nF terms |
PoE pins of the magjack: leave **unloaded / NC** (no PoE in this design).
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## 9. RTC
| Net | Part | Notes |
|-----|------|-------|
| RTC_SDA/SCL | CM5 I2C (dedicated RTC I2C on CM5) | CM5 has internal RTC; carrier provides battery backup |
| +VRTC | CR2032 via BT1 | back-up to CM5 RTC battery pin |
> CM5 has an **on-module RTC**; the carrier mainly provides the **CR2032 backup cell** to the CM5 RTC battery input (per CM5IO reference). If an *external* I²C RTC is also wanted (redundancy), add e.g. PCF85063A on a GPIO I²C — optional, default is just the coin cell to CM5.
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## 10. Bill of Materials (per board) — candidate MPNs
| 12 | ESD_USB | 3 | USB ESD array | ST USBLC6-2SC6 | 0.15 ea |
| 13 | U_VBUS | 1 | USB VBUS current-limit switch | TI TPS2552 / AP22653 | 0.5–1 |
| 14 | U_SCHMITT | 1 | Single Schmitt buffer 3V3 | TI SN74LVC1G17 | 0.1 |
| 15 | ~~U_LVLSHIFT~~ | 0 | **REMOVED** — SYNC is 3.3 V, no translation needed (correction C1). Replace with one 0402 series R (in passives). | — | — |
| 16 | TVS_PPS | 1 | Low-cap TVS on PPS in | ESD9B / PESD | 0.1 |
3. PCIe **RX is NOT coupled on the carrier** — caps live on the M.2 card's TX (standard M.2); CM5 couples its own TX. (Corrected: earlier text/BOM said carrier-side; double-coupling would break the link.)
