Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
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|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(symbol "power:PWR_FLAG"
|
|
|
|
|
(power global)
|
|
|
|
|
(pin_numbers
|
|
|
|
|
(hide yes)
|
|
|
|
|
)
|
|
|
|
|
(pin_names
|
|
|
|
|
(offset 0)
|
|
|
|
|
(hide yes)
|
|
|
|
|
)
|
|
|
|
|
(exclude_from_sim no)
|
|
|
|
|
(in_bom yes)
|
|
|
|
|
(on_board yes)
|
|
|
|
|
(in_pos_files yes)
|
|
|
|
|
(duplicate_pin_numbers_are_jumpers no)
|
|
|
|
|
(property "Reference" "#FLG"
|
|
|
|
|
(at 0 1.905 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Value" "PWR_FLAG"
|
|
|
|
|
(at 0 3.81 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Footprint" ""
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Datasheet" ""
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Description" "Special symbol for telling ERC where power comes from"
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "ki_keywords" "flag power"
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(symbol "PWR_FLAG_0_0"
|
|
|
|
|
(pin power_out line
|
|
|
|
|
(at 0 0 90)
|
|
|
|
|
(length 0)
|
|
|
|
|
(name ""
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "1"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(symbol "PWR_FLAG_0_1"
|
|
|
|
|
(polyline
|
|
|
|
|
(pts
|
|
|
|
|
(xy 0 0) (xy 0 1.27) (xy -1.016 1.905) (xy 0 2.54) (xy 1.016 1.905) (xy 0 1.27)
|
|
|
|
|
)
|
|
|
|
|
(stroke
|
|
|
|
|
(width 0)
|
|
|
|
|
(type default)
|
|
|
|
|
)
|
|
|
|
|
(fill
|
|
|
|
|
(type none)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(embedded_fonts no)
|
|
|
|
|
)
|
|
|
|
|
(symbol "Connector:Bus_M.2_Socket_E"
|
|
|
|
|
(exclude_from_sim no)
|
|
|
|
|
(in_bom yes)
|
|
|
|
|
(on_board yes)
|
|
|
|
|
(in_pos_files yes)
|
|
|
|
|
(duplicate_pin_numbers_are_jumpers no)
|
|
|
|
|
(property "Reference" "J"
|
|
|
|
|
(at -22.86 46.99 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
(justify left)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Value" "Bus_M.2_Socket_E"
|
|
|
|
|
(at 16.51 46.99 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Footprint" ""
|
|
|
|
|
(at 0 26.67 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Datasheet" "https://web.archive.org/web/20200613074028/http://read.pudn.com/downloads794/doc/project/3133918/PCIe_M.2_Electromechanical_Spec_Rev1.0_Final_11012013_RS_Clean.pdf#page=150"
|
|
|
|
|
(at 0 12.7 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "Description" "M.2 Socket 1-SD Mechanical Key E"
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "ki_keywords" "M2 NGNF PCI-E"
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(property "ki_fp_filters" "*M*2*E*"
|
|
|
|
|
(at 0 0 0)
|
|
|
|
|
(show_name no)
|
|
|
|
|
(do_not_autoplace no)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(symbol "Bus_M.2_Socket_E_0_1"
|
|
|
|
|
(rectangle
|
|
|
|
|
(start -22.86 45.72)
|
|
|
|
|
(end 22.86 -45.72)
|
|
|
|
|
(stroke
|
|
|
|
|
(width 0.254)
|
|
|
|
|
(type default)
|
|
|
|
|
)
|
|
|
|
|
(fill
|
|
|
|
|
(type background)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(symbol "Bus_M.2_Socket_E_1_1"
|
|
|
|
|
(pin power_in line
|
|
|
|
|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "GND"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "1"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin power_in line
|
|
|
|
|
(at 0 48.26 270)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "3.3V"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "2"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at -25.4 10.16 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "USB_D+"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "3"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at 0 48.26 270)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(name "3.3V"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "4"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at -25.4 7.62 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "USB_D-"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "5"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin open_collector line
|
|
|
|
|
(at 25.4 -20.32 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "~{LED_1}"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "6"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(name "GND"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "7"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at 25.4 7.62 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "PCM_CLK/I2S_SCK"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "8"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at -25.4 -12.7 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "SDIO_CLK"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "9"
|
|
|
|
|
(effects
|
|
|
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
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(pin bidirectional line
|
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(at 25.4 5.08 180)
|
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(length 2.54)
|
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(name "PCM_SYNC/I2S_WS"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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(number "10"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
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(pin bidirectional line
|
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(at -25.4 -15.24 0)
|
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(length 2.54)
|
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(name "SDIO_CMD"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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(number "11"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
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(pin input line
|
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|
(at 25.4 2.54 180)
|
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|
(length 2.54)
|
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(name "PCM_IN/I2S_SD_IN"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
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)
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(number "12"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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)
|
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(pin bidirectional line
|
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|
(at -25.4 -17.78 0)
|
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|
|
(length 2.54)
|
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|
|
(name "SDIO_DATA0"
|
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|
|
(effects
|
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|
(font
|
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|
(size 1.27 1.27)
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|
)
|
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)
|
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)
|
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(number "13"
|
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|
(effects
|
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|
(font
|
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|
(size 1.27 1.27)
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)
|
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)
|
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|
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)
|
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|
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)
|
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|
|
(pin output line
|
|
|
|
|
(at 25.4 0 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "PCM_OUT/I2S_SD_OUT"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
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|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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)
|
|
|
|
|
)
|
|
|
|
|
(number "14"
|
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|
|
(effects
|
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|
|
(font
|
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|
(size 1.27 1.27)
|
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|
|
)
|
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|
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)
|
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|
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)
|
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|
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)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at -25.4 -20.32 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "SDIO_DATA1"
|
|
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|
|
(effects
|
|
|
|
|
(font
|
|
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|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "15"
|
|
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|
|
(effects
|
|
|
|
|
(font
|
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|
|
(size 1.27 1.27)
|
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|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin open_collector line
|
|
|
|
|
(at 25.4 -22.86 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "~{LED_2}"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "16"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at -25.4 -22.86 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "SDIO_DATA2"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "17"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(name "GND"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "18"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
|
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|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at -25.4 -25.4 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "SDIO_DATA3"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "19"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin input line
|
|
|
|
|
(at 25.4 -5.08 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "~{UART_WAKE}"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "20"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin input line
|
|
|
|
|
(at -25.4 -27.94 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "~{SDIO_WAKE}"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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|
)
|
|
|
|
|
)
|
|
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|
|
(number "21"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin input line
|
|
|
|
|
(at 25.4 -7.62 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "UART_RXD"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
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|
|
)
|
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)
|
|
|
|
|
)
|
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|
|
(number "22"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
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|
|
)
|
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|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at -25.4 -30.48 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "~{SDIO_RESET}"
|
|
|
|
|
(effects
|
|
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|
|
(font
|
|
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|
|
(size 1.27 1.27)
|
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|
|
)
|
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|
)
|
|
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|
|
)
|
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|
|
(number "23"
|
|
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|
|
(effects
|
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|
|
(font
|
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|
(size 1.27 1.27)
|
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|
|
)
|
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)
|
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|
)
|
|
|
|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at 25.4 -10.16 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "UART_TXD"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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|
)
|
|
|
|
|
)
|
|
|
|
|
(number "32"
|
|
|
|
|
(effects
|
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|
|
|
(font
|
|
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|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(name "GND"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "33"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
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|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin input line
|
|
|
|
|
(at 25.4 -12.7 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "UART_CTS"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "34"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
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|
|
)
|
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|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at -25.4 33.02 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "PETp0"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "35"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
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|
|
)
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at 25.4 -15.24 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "UART_RTS"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "36"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at -25.4 30.48 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "PETn0"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "37"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at 25.4 38.1 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "VENDOR_DEFINED"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(number "38"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin passive line
|
|
|
|
|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(name "GND"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
|
|
|
|
(size 1.27 1.27)
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)
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)
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)
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(number "39"
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(effects
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(font
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(size 1.27 1.27)
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)
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(pin passive line
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(at 25.4 35.56 180)
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(length 2.54)
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(name "VENDOR_DEFINED"
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(effects
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(font
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(size 1.27 1.27)
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)
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(number "40"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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(pin output line
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(at -25.4 27.94 0)
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(length 2.54)
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(name "PERp0"
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(effects
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(font
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(size 1.27 1.27)
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)
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(number "41"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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(pin passive line
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(at 25.4 33.02 180)
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(length 2.54)
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(name "VENDOR_DEFINED"
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(effects
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(font
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(size 1.27 1.27)
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)
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(number "42"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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(pin output line
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(at -25.4 25.4 0)
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(length 2.54)
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(name "PERn0"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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(number "43"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
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(pin bidirectional line
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(at 25.4 -38.1 180)
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(length 2.54)
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(name "COEX3"
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(effects
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(font
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(size 1.27 1.27)
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)
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(number "44"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
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(pin passive line
|
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(at 0 -48.26 90)
|
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(length 2.54)
|
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(hide yes)
|
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(name "GND"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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(number "45"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
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(pin bidirectional line
|
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(at 25.4 -35.56 180)
|
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(length 2.54)
|
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(name "COEX2"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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(number "46"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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)
|
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(pin passive line
|
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|
|
|
(at -25.4 -35.56 0)
|
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|
|
(length 2.54)
|
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(name "REFCLKp0"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
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(number "47"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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)
|
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(pin bidirectional line
|
|
|
|
|
(at 25.4 -33.02 180)
|
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|
|
(length 2.54)
|
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|
(name "COEX1"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
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)
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(number "48"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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)
|
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(pin passive line
|
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|
(at -25.4 -38.1 0)
|
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|
|
(length 2.54)
|
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(name "REFCLKn0"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
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(number "49"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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)
|
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(pin output line
|
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|
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|
(at 25.4 -27.94 180)
|
|
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|
|
(length 2.54)
|
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(name "SUSCLK"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
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(number "50"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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)
|
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(pin passive line
|
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|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
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|
|
(name "GND"
|
|
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(effects
|
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|
(font
|
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|
(size 1.27 1.27)
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)
|
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)
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)
|
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(number "51"
|
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(effects
|
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(font
|
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(size 1.27 1.27)
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)
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)
|
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)
|
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)
|
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(pin passive line
|
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|
(at -25.4 43.18 0)
|
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|
|
(length 2.54)
|
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(name "~{PERST0}"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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(number "52"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
|
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)
|
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(pin output line
|
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|
|
(at -25.4 40.64 0)
|
|
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|
|
(length 2.54)
|
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|
|
(name "~{CLKREQ0}"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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(number "53"
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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(pin output line
|
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(at 25.4 15.24 180)
|
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|
|
(length 2.54)
|
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(name "~{W_DISABLE2}"
|
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(effects
|
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(font
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(size 1.27 1.27)
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)
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)
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(number "54"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
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)
|
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(pin output line
|
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|
(at -25.4 38.1 0)
|
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|
|
(length 2.54)
|
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(name "~{PEWAKE0}"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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(number "55"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
|
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)
|
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(pin output line
|
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|
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|
(at 25.4 17.78 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "~{W_DISABLE1}"
|
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|
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(effects
|
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(font
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(size 1.27 1.27)
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)
|
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)
|
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(number "56"
|
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(effects
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(font
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(size 1.27 1.27)
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)
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)
|
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)
|
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|
|
(pin passive line
|
|
|
|
|
(at 0 -48.26 90)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(hide yes)
|
|
|
|
|
(name "GND"
|
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|
|
(effects
|
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|
(font
|
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(size 1.27 1.27)
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)
|
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)
|
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)
|
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(number "57"
|
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|
(effects
|
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(font
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(size 1.27 1.27)
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)
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)
|
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)
|
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|
|
)
|
|
|
|
|
(pin bidirectional line
|
|
|
|
|
(at 25.4 27.94 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "I2C_DATA"
|
|
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|
|
(effects
|
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(font
|
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(size 1.27 1.27)
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)
|
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)
|
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)
|
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|
(number "58"
|
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|
(effects
|
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(font
|
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|
(size 1.27 1.27)
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)
|
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)
|
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|
)
|
|
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|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at -25.4 22.86 0)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "RESERVED/PETp1"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
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(size 1.27 1.27)
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)
|
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)
|
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)
|
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|
|
(number "59"
|
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|
|
(effects
|
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(font
|
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|
(size 1.27 1.27)
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)
|
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)
|
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|
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)
|
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|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at 25.4 25.4 180)
|
|
|
|
|
(length 2.54)
|
|
|
|
|
(name "I2C_CLK"
|
|
|
|
|
(effects
|
|
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|
|
(font
|
|
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|
(size 1.27 1.27)
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|
)
|
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)
|
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|
|
)
|
|
|
|
|
(number "60"
|
|
|
|
|
(effects
|
|
|
|
|
(font
|
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|
|
|
(size 1.27 1.27)
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|
|
)
|
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|
|
)
|
|
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|
|
)
|
|
|
|
|
)
|
|
|
|
|
(pin output line
|
|
|
|
|
(at -25.4 20.32 0)
|
|
|
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(at 170.18 105.41 0)
|
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(unit 1)
|
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(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
2026-07-04 09:35:29 -04:00
|
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|
(uuid "9cfd8f15-0052-56b6-a872-7bc1d714bd78")
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(property "Reference" "J_E1" (at 170 53 0) (effects (font (size 1.27 1.27))))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
(property "Value" "M.2_Ekey_WiFi" (at 170 55 0) (effects (font (size 1.27 1.27))))
|
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(property "Footprint" "Connector_PCBEdge:M.2_2230-xx-E" (at 170 105 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
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(property "Datasheet" "" (at 170 105 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
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(property "Description" "M.2 A+E key socket, Wi-Fi (AsiaRF AW7915/MT7915)" (at 170 105 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
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(pin "1" (uuid "67f6c68f-89af-58e5-b824-e199f534ccb5"))
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(pin "2" (uuid "94996e33-6fc1-5e74-b687-575bf3acbba3"))
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(pin "3" (uuid "17794531-5c7c-53c1-b2d6-739daca38d5d"))
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(pin "4" (uuid "1b13e455-e30a-50c5-bc87-6a9634db7141"))
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(pin "5" (uuid "28191e63-d1d6-5d9b-a5f3-b0619f125f01"))
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(pin "6" (uuid "28c368d2-1fae-5866-9a51-412a097f5d53"))
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(pin "7" (uuid "c7d493d8-3169-5eab-b943-bd664c09f285"))
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(pin "8" (uuid "3a6ea6f4-a8b3-5009-a7cc-d6f182e4e30a"))
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(pin "9" (uuid "3e59021d-ee33-56d9-a92c-c22764c182c8"))
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(pin "10" (uuid "e6b76f41-f572-57d9-84fe-bc97dbb0f585"))
|
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(pin "11" (uuid "c34ebc5b-d353-573a-9ae1-3e840566d99e"))
|
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(pin "12" (uuid "9cc8f1c1-149f-5b14-ae43-0366491e4a59"))
|
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(pin "13" (uuid "082cd125-2758-5abb-b947-e871ae25b8b9"))
|
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(pin "14" (uuid "0977d18e-1928-5b42-9fc2-775da13c73b2"))
|
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(pin "15" (uuid "174da418-69f0-5305-826a-bf2889ebb008"))
|
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(pin "16" (uuid "57012303-4953-5f09-ba0c-357dc5dcbac9"))
|
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(pin "17" (uuid "c244f461-7115-554d-9226-3dc2759efab9"))
|
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(pin "18" (uuid "c2ca9d8a-224a-598a-8f04-995bafc088d2"))
|
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(pin "19" (uuid "168506e2-9a73-5e06-98ce-4b70f187af07"))
|
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(pin "20" (uuid "5026c557-229e-5f44-a69f-5e8126e5719d"))
|
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(pin "21" (uuid "5f6e78a1-794c-51a8-a160-c1d2e4731b12"))
|
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(pin "22" (uuid "8925728e-bbaf-5df7-8e9b-80d7ab3e45af"))
|
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(pin "23" (uuid "edd6d257-4881-57b4-a6a5-88ad5a6b65eb"))
|
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(pin "32" (uuid "3c488d31-b9a8-5d72-b324-2cae3e78d610"))
|
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(pin "33" (uuid "47bc834f-6d46-5498-a846-aa8bd76bbb33"))
|
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(pin "34" (uuid "7210b861-494d-579f-92c6-7bdc11dc962e"))
|
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(pin "35" (uuid "02b18f30-8e1d-515f-970e-ccad575f55d1"))
|
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(pin "36" (uuid "6e747150-b180-565f-9f66-1e42d50c8f59"))
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|
(pin "37" (uuid "c3082882-773b-5fc0-acec-c614a9f0889f"))
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(pin "38" (uuid "90284202-aa00-5791-a3d7-f2d9c6c67c80"))
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(pin "39" (uuid "233e2b8a-3514-5183-a2a8-4bf2162caf54"))
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(pin "40" (uuid "d550cafa-a0aa-5b6b-9cb7-02994c576adc"))
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(pin "41" (uuid "2a2d3dc8-b1ff-58a6-8ad7-0b79e2e09618"))
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(pin "42" (uuid "3cbc259c-eec6-539c-b3fa-d08bc0a4bbc2"))
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(pin "43" (uuid "87ad49dc-3d35-5de1-8546-6a3f5f46d1dd"))
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(pin "44" (uuid "6f756325-dcf3-54f6-838a-e2bd2138beb7"))
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(pin "45" (uuid "38356409-3951-5e25-88b1-b678af4d66d6"))
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(pin "46" (uuid "72ffb188-6dab-5f75-83ad-47b13d25af40"))
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(pin "47" (uuid "bf90cde4-9870-51a8-89a1-36d0439a1dfd"))
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(pin "48" (uuid "069f2d54-b280-568c-9737-698e955fab76"))
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(pin "49" (uuid "a9ac5450-854a-57bc-b667-71ff642c1e1e"))
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(pin "50" (uuid "6c10a126-4dc6-5b6a-be0e-21f7e283d0f0"))
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(pin "51" (uuid "8b98aa58-fc6c-50eb-808a-e3d62fd3e30e"))
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(pin "52" (uuid "a1aa6fc6-98e9-57e9-a2df-f78b01bae35d"))
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(pin "53" (uuid "a476f0d7-24ad-5343-94be-13b8d9621a15"))
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(pin "54" (uuid "06701153-1d35-5630-a990-130fb96e1a0a"))
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(pin "55" (uuid "ad998a2d-e341-59e5-8244-cda9349a278e"))
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(pin "56" (uuid "aa4fafed-efe9-595c-b84d-6f21a47b56a9"))
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(pin "57" (uuid "8edd3e53-a7a6-560d-a803-25639fa0444c"))
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(pin "58" (uuid "31c931d7-7abd-503e-bf53-4d2437711308"))
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(pin "59" (uuid "184a0e44-275c-571e-b114-c27c200f4a32"))
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(pin "60" (uuid "9fee4e70-d377-573a-bac5-0736d517d3cb"))
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(pin "61" (uuid "3f9fc84a-8f89-56e1-8c28-61963f1596d1"))
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(pin "62" (uuid "572573d3-6b43-502e-bc74-ba26a2c8b0b9"))
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(pin "63" (uuid "8c4c6e70-7ea3-51ed-9f15-f322f38819a3"))
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(pin "64" (uuid "3f137b9b-8fe9-5bb8-b465-3dae2ff19394"))
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(pin "65" (uuid "f88bd783-89fe-5631-8654-deb5d1f4f0b0"))
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(pin "66" (uuid "1956ad86-a222-5bcf-a23a-b7017faed066"))
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(pin "67" (uuid "492be341-798b-5491-9256-3c5b281a66b6"))
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(pin "68" (uuid "afcfda9b-3d3f-59b3-a891-8d1ca3a7469d"))
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(pin "69" (uuid "6bd941df-ee75-5c65-8b49-8de90891a1e1"))
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(pin "70" (uuid "3ba0f684-7ec3-545c-809c-126e330b924b"))
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(pin "71" (uuid "80daa6ee-a1bc-56cb-96e5-a971afa8509f"))
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(pin "72" (uuid "b6bc8337-909b-5a7b-8235-08905ec8797a"))
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(pin "73" (uuid "4d023968-563b-594c-8828-90b959a69fbc"))
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(pin "74" (uuid "3feab80a-f23d-57f7-be7f-16fb7efc0cc4"))
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(pin "75" (uuid "8e0a1780-b855-573b-93d8-0cb618e05b8e"))
|
2026-07-04 09:35:29 -04:00
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|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "J_E1") (unit 1))))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
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)
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(global_label "PCIE_TX_P"
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(shape input)
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(at 144.78 72.39 90)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "f6e0bce8-8673-592f-9401-43bd437f3ad6")
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)
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(global_label "PCIE_TX_N"
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(shape input)
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(at 144.78 74.93 90)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "15cd8d90-b4b8-5901-88fd-cbc9781f2a4c")
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)
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(global_label "PCIE_RX_P"
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(shape input)
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(at 144.78 77.47 90)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "fc5f3d02-68db-5e5f-bbed-2bfdc708f07a")
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)
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(global_label "PCIE_RX_N"
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(shape input)
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(at 144.78 80.01 180)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "85f2ee6f-fb5d-51fd-9350-e9975097c119")
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)
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(global_label "PCIE_CLK_P"
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(shape input)
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(at 144.78 140.97 270)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "db5d4844-9769-52b8-a0c9-d0b946447166")
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)
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(global_label "PCIE_CLK_N"
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(shape input)
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(at 144.78 143.51 270)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "86756717-9e34-527e-bd67-1530aa10b1ef")
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)
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(global_label "PCIE_nRST"
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(shape input)
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(at 144.78 62.23 90)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "92276086-3dfe-5013-9704-dd10ad5394bc")
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)
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(global_label "PCIE_nCLKREQ"
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(shape input)
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(at 144.78 64.77 90)
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(effects (font (size 1.27 1.27)) (justify left))
|
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(uuid "d6fddfc2-5c36-5dfe-a3f5-d41f3aa2d07f")
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)
|
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|
|
(global_label "PCIE_nWAKE"
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(shape input)
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(at 144.78 67.31 90)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "eb820fe5-24c6-5dc0-8f4d-e2a59ca8714e")
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)
|
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|
|
(global_label "+3V3_RF"
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(shape input)
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|
(at 170.18 57.15 90)
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(effects (font (size 1.27 1.27)) (justify left))
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(uuid "920aac2f-edcd-52ef-904a-1d79bf664b16")
|
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)
|
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|
|
(global_label "+3V3_RF"
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(shape input)
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|
(at 170.18 57.15 90)
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|
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|
(effects (font (size 1.27 1.27)) (justify left))
|
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(uuid "920aac2f-edcd-52ef-904a-1d79bf664b16")
|
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)
|
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|
|
(global_label "+3V3_RF"
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(shape input)
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(at 170.18 57.15 90)
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(effects (font (size 1.27 1.27)) (justify left))
|
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(uuid "920aac2f-edcd-52ef-904a-1d79bf664b16")
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)
|
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|
|
(global_label "+3V3_RF"
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(shape input)
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(at 170.18 57.15 90)
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|
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(effects (font (size 1.27 1.27)) (justify left))
|
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(uuid "920aac2f-edcd-52ef-904a-1d79bf664b16")
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)
|
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|
|
(label "WIFI_DISABLE#"
|
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|
(at 195.58 87.63 0)
|
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|
(effects (font (size 1.27 1.27)) (justify left))
|
|
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|
|
(uuid "56ab75fb-7daa-533d-850a-21f07ab90588")
|
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)
|
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|
(label "WIFI_DISABLE2#"
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(at 195.58 90.17 0)
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(effects (font (size 1.27 1.27)) (justify left))
|
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|
(uuid "8113565d-fa7a-5956-882a-613fe5b80032")
|
|
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)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
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|
|
(at 170.18 153.67 0)
|
|
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|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "481ca82b-f7c6-5672-b33b-0dffb91079c3")
|
|
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|
|
(property "Reference" "#PWR1" (at 170.18 156.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
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|
|
(property "Value" "GND" (at 170.18 155.67 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "9fa67fa0-986a-5b46-aab5-cf8e3f7224c7"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWR1") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 170.18 153.67 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "8773a784-9f33-5106-8c39-44e7e62ddcd2")
|
|
|
|
|
(property "Reference" "#PWR7" (at 170.18 156.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Value" "GND" (at 170.18 155.67 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "3012c969-75fc-564b-a911-7c9a70ce983b"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWR7") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 170.18 153.67 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "6aa76b94-ef82-537b-8daf-91201d33cb3e")
|
|
|
|
|
(property "Reference" "#PWR18" (at 170.18 156.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Value" "GND" (at 170.18 155.67 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "859399c9-c65a-583b-bd88-802041f668e3"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWR18") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 170.18 153.67 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "d7f470a9-88da-54d3-b057-c9d53408efe2")
|
|
|
|
|
(property "Reference" "#PWR33" (at 170.18 156.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Value" "GND" (at 170.18 155.67 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "21b3b202-3652-5102-965d-75fbb0dd4ec8"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWR33") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 170.18 153.67 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "c517cc56-37a3-5315-93a7-4506474de5a2")
|
|
|
|
|
(property "Reference" "#PWR39" (at 170.18 156.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Value" "GND" (at 170.18 155.67 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 170.18 153.67 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "2bb53e4a-9791-5cef-b800-d1c26e3c5e84"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWR39") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 170.18 153.67 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
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(at 214.63 106.68 90)
|
|
|
|
|
(effects (font (size 1.27 1.27)) (justify left))
|
|
|
|
|
(uuid "ce950d44-a7c2-575c-8ab5-789e2411833b")
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 214.63 114.3 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
2026-07-04 09:35:29 -04:00
|
|
|
(uuid "fc3f2eea-dc38-5565-8d22-180c3e7a31bd")
|
|
|
|
|
(property "Reference" "#PWRC_E1g1" (at 214.63 117.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
(property "Value" "GND" (at 214.63 116.3 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 214.63 114.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 214.63 114.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
2026-07-04 09:35:29 -04:00
|
|
|
(pin "1" (uuid "477507a7-dd98-57ff-a0c7-78bb4bc6759f"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWRC_E1g1") (unit 1))))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "Device:C")
|
|
|
|
|
(at 222.25 110.49 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "c353a3ee-b20c-55ca-a740-bf16913dc00b")
|
|
|
|
|
(property "Reference" "C_E2" (at 224.79 109.49 0) (effects (font (size 1.27 1.27)) (justify left)))
|
|
|
|
|
(property "Value" "100n" (at 224.79 111.49 0) (effects (font (size 1.27 1.27)) (justify left)))
|
|
|
|
|
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (at 222.25 110.49 90) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 222.25 110.49 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "612a6e11-2a58-559a-a046-0a34142c2f08"))
|
|
|
|
|
(pin "2" (uuid "b8f142af-dda2-52a5-99ee-59a25abee08b"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "C_E2") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(global_label "+3V3_RF"
|
|
|
|
|
(shape input)
|
|
|
|
|
(at 222.25 106.68 90)
|
|
|
|
|
(effects (font (size 1.27 1.27)) (justify left))
|
|
|
|
|
(uuid "766c27ee-52c9-59ac-a662-53fa8acf2014")
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 222.25 114.3 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
2026-07-04 09:35:29 -04:00
|
|
|
(uuid "8880f2d0-fa49-5451-9445-120a7162fc7b")
|
|
|
|
|
(property "Reference" "#PWRC_E2g1" (at 222.25 117.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
(property "Value" "GND" (at 222.25 116.3 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 222.25 114.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 222.25 114.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
2026-07-04 09:35:29 -04:00
|
|
|
(pin "1" (uuid "0e0779c5-5cde-5daa-91bf-5b61d357cb25"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWRC_E2g1") (unit 1))))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "Device:C")
|
|
|
|
|
(at 229.87 110.49 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
|
|
|
|
(uuid "721fe193-5e8e-53a2-abe0-54bef161e075")
|
|
|
|
|
(property "Reference" "C_E3" (at 232.41 109.49 0) (effects (font (size 1.27 1.27)) (justify left)))
|
|
|
|
|
(property "Value" "100n" (at 232.41 111.49 0) (effects (font (size 1.27 1.27)) (justify left)))
|
|
|
|
|
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (at 229.87 110.49 90) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 229.87 110.49 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(pin "1" (uuid "75060c03-4cf3-5a5a-a5b9-5ebfdc43fb60"))
|
|
|
|
|
(pin "2" (uuid "e1f111cc-0ccb-5624-a53c-916073c084af"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "C_E3") (unit 1))))
|
|
|
|
|
)
|
|
|
|
|
(global_label "+3V3_RF"
|
|
|
|
|
(shape input)
|
|
|
|
|
(at 229.87 106.68 90)
|
|
|
|
|
(effects (font (size 1.27 1.27)) (justify left))
|
|
|
|
|
(uuid "6dfd446a-6542-51e4-8a7d-7d13cddba859")
|
|
|
|
|
)
|
|
|
|
|
(symbol
|
|
|
|
|
(lib_id "power:GND")
|
|
|
|
|
(at 229.87 114.3 0)
|
|
|
|
|
(unit 1)
|
|
|
|
|
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
|
2026-07-04 09:35:29 -04:00
|
|
|
(uuid "a1a7410f-74ff-5776-850d-1b5bd9d7abfc")
|
|
|
|
|
(property "Reference" "#PWRC_E3g1" (at 229.87 117.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
(property "Value" "GND" (at 229.87 116.3 0) (effects (font (size 1.27 1.27))))
|
|
|
|
|
(property "Footprint" "" (at 229.87 114.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
|
|
|
|
(property "Datasheet" "" (at 229.87 114.3 0) (effects (font (size 1.27 1.27)) (hide yes)))
|
2026-07-04 09:35:29 -04:00
|
|
|
(pin "1" (uuid "baf3d2ab-371e-5ce8-9eaf-c20627ee3dcf"))
|
|
|
|
|
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWRC_E3g1") (unit 1))))
|
Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes
First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).
- PCIe link-0 wired to the 9 freed CM5 pins via global labels
(TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
(106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
pins + by-name labels; grid-snap; cross-connector ERC pin retyping)
Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.
Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-30 14:58:09 -04:00
|
|
|
)
|
|
|
|
|
(sheet_instances
|
|
|
|
|
(path "/"
|
|
|
|
|
(page "4")
|
|
|
|
|
)
|
|
|
|
|
)
|
|
|
|
|
)
|