add controls to lvx

LVX6048/2026-04-26-parallel.md

@@ -99,8 +99,11 @@ small patches.
 ## Files touched
 
 ```
-M  LVX6048/powermon-patches/pi18.py            (MOD 06 -> "Charge"; parallel_instance_number decoder fix)
-M  LVX6048/lvx-flash/flash.py                  (parallel_instance_number index semantics; new sync-check rules)
+M  LVX6048/README.md                           (status section rewrite, sensor count, hot-plug note)
+M  LVX6048/powermon-patches/pi18.py            (MOD 06; GS instance-index decoder; PGS validity flag;
+                                                two PGS fields named: battery V + capacity)
+M  LVX6048/lvx-flash/flash.py                  (instance-index semantics; sync-check rule rewrite;
+                                                cutoff <= stop_discharge validator)
 M  LVX6048/bin/lvx-resolve-links               (retry loop for hot-plug race)
 M  LVX6048/etc/udev/rules.d/99-lvx6048.rules   (ACTION=="add" RUN+= cascade)
 A  LVX6048/2026-04-26-lvx6048_1-dump           (post-commissioning baseline)
@@ -127,13 +130,48 @@ Pass criteria post-commissioning:
 - battery V agreement within ~0.2 V
 - charge currents within ~5 A symmetric (when both are charging)
 
-## Loose ends / next pass
+## Nice-to-have pass
 
-1. update `LVX6048/README.md` "Next steps" section to reflect that
-   parallel commissioning + decoder + hot-plug fixes are done, and
-   the slave-firmware delta is intentionally unrepaired (benign)
-2. (optional) verify MOD 06 label by observing in different states
-3. (optional) decode remaining PGS fields now that values are meaningful
-4. (optional, longer horizon) closed-loop BMS comms via the dedicated
-   pack→inverter CAN port; defer until open-loop has been stable for a
-   week and we can baseline SoC accuracy
+12. **README "Status / pending" section rewritten.** Replaced the stale
+    "Next steps / not done" with current state — parallel commissioning
+    done, slave-fw delta intentional, hot-plug recovery automatic.
+    Also bumped the per-inverter sensor count from 29 → 23 in the
+    architecture diagram (post-MQTT-cleanup) and added a "cable moves
+    and inverter power-cycles" paragraph noting the udev auto-recovery.
+
+13. **PGS partial decode (two confirmed fields).** Captured PGS0+PGS1
+    on both units while operating in parallel and cross-referenced
+    against simultaneous GS readings to identify two previously-raw
+    fields:
+    - field_14 (idx 13) → `Battery voltage (parallel view)` — V*10
+    - field_18 (idx 17) → `Battery capacity (parallel view)` — %
+    Several others have plausible candidates noted in the source
+    comment (charging current, mppt voltage) but couldn't be confirmed
+    without captures under load and during discharge. PGS isn't being
+    polled by powermon today, so naming these doesn't change HA — it
+    just makes future use of the command (or extending the pollers) cleaner.
+
+14. **PGS field 0 reverted from the GS fix.** The `Parallel instance
+    number` field has different semantics in PGS than in GS — live
+    captures show PGS field 0 always returns "1" regardless of the
+    queried instance, so it's a "valid response" flag, not the index.
+    Kept the index labeling on GS (where it really is the unit's own
+    instance number) and reverted PGS to the simpler 2-value flag.
+
+15. **`flash.py apply` round-trip verified.** Ran `flash.py diff` /
+    `apply --confirm` against the live state with the
+    `eg4-lp4-v2.yaml` profile — diff reports no changes, apply
+    correctly says "nothing to do", `compare` afterward shows 12/12
+    settings still identical. Validates the apply code path end-to-end
+    on a no-op. Caught one validator bug along the way — `cutoff <
+    stop_discharge` was strict but the inverter actually accepts
+    `cutoff == stop_discharge` (which the user has set). Loosened to
+    `cutoff <= stop_discharge`.
+
+## Still pending
+
+- (optional) verify MOD 06 label by observing in non-charging states
+- (optional) finish PGS decode: capture under load + during discharge
+- (optional, longer horizon) closed-loop BMS comms via the dedicated
+  pack→inverter CAN port; defer until open-loop has been stable for a
+  week and we can baseline SoC accuracy