1d169476fb
Drops the unused M.2 M-key/NVMe block — design is 1x M.2 E-key (Wi-Fi) only, since the CM5 exposes a single PCIe x1 lane (datasheet SC1466), reserved for the E-key. The 10 freed PCIE_* lanes are NC on Module1 unit 2, to be rewired to a fresh E-key sheet in the add phase. - CM5_HighSpeed: retire PCIE_* labels/wires, NC pins 102,104,106,109, 110,112,116,118,122,124 - root CM5IO: drop whole PCIe-M2 (sheet) block; strip dangling PCIE_* pins off the kept CM5_HighSpeed sheet symbol - delete carrier/PCIe-M2.kicad_sch; clean .kicad_pro sheets array + ERC exclusion - retire_block.py: add --drop-sheet FILE (remove whole (sheet) block + sheet_instances path) - analysis/baseline/carrier_stripped.json: new add-phase diff anchor Verify: ERC 136->133 (zero new violation types); analyzer diff +0/~0 (cumulative -41 removed vs original ref); netlist confirms +5v/+3.3v/ GND/+1.8v intact (U8's M2_3v3 was a local rail, not board +3.3v). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
289 lines
14 KiB
Python
289 lines
14 KiB
Python
#!/usr/bin/env python3
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"""retire_block.py — remove a circuit block from a CM5-carrier KiCad sheet cleanly.
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For the diff-from-reference port (see .claude/skills/kicad-port). Given a sheet and a
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set of reference designators to drop plus the net-name globs they own, this:
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1. excises each named (symbol ...) block (paren-matched, by Reference property),
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2. floods the retired nets from their (label ...) coords through (wire ...) segments,
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3. removes those labels + every wire in the flooded nets,
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4. places (no_connect ...) markers on the exposed module pins that sat on those nets,
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5. writes back only if parentheses stay balanced.
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Module pin coordinates are computed from the lib_symbol pin locals + the placement
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transform (validated abs = origin + (lx, -ly) for rot0/no-mirror; other orientations
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are rejected rather than guessed). Idempotent-ish: re-running finds nothing to do.
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Usage:
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python3 tools/retire_block.py <sheet.kicad_sch> \
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--symbols J7,U18 --nets 'SD_*' \
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--module-lib CM5IO:ComputeModule5-CM5 [--apply]
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Without --apply it's a dry run (prints the plan, writes nothing).
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"""
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import re, sys, argparse, fnmatch, math, uuid as uuidlib
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S = r'\s*'
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def xform(px, py, rot, mirror, lx, ly):
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"""Schematic abs coord of a lib pin local (lx,ly) for a placement. Validated:
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mirror, then CCW rotate, then lib-Y-up -> schematic-Y-down flip."""
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X, Y = lx, ly
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if mirror == 'y': X = -X
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if mirror == 'x': Y = -Y
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r = math.radians(rot)
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rx = X * math.cos(r) - Y * math.sin(r)
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ry = X * math.sin(r) + Y * math.cos(r)
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return (round(px + rx, 2), round(py - ry, 2))
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def paren_end(t, s):
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d = 0
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for i in range(s, len(t)):
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if t[i] == '(': d += 1
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elif t[i] == ')':
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d -= 1
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if d == 0: return i + 1
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raise ValueError("unbalanced from offset %d" % s)
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def fnum(x): return round(float(x), 2)
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def find_symbol_blocks(t):
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"""Yield (start,end,reference) for every placed (symbol (lib_id ...)) block."""
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for m in re.finditer(r'\(symbol' + S + r'\(lib_id' + S + r'"', t):
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s = m.start(); e = paren_end(t, s); seg = t[s:e]
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ref = re.search(r'\(property' + S + r'"Reference"' + S + r'"([^"]+)"', seg)
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if ref: yield (s, e, ref.group(1))
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def module_pins_abs(t, module_lib):
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"""Compute {pin_number:(x,y)} for the placed module instance on this sheet."""
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inst = re.search(r'\(symbol' + S + r'\(lib_id' + S + r'"' + re.escape(module_lib) + r'"\)(.{0,500}?)\(unit' + S + r'(\d+)\)', t, re.S)
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if not inst: return {}, None
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body, unit = inst.group(1), inst.group(2)
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at = re.search(r'\(at' + S + r'([\d.-]+)' + S + r'([\d.-]+)' + S + r'([\d.-]+)\)', body)
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mir = re.search(r'\(mirror' + S + r'(\w+)\)', body)
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px, py, rot = float(at.group(1)), float(at.group(2)), float(at.group(3))
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if rot != 0 or mir:
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sys.exit(f"REFUSING: module instance has rot={rot} mirror={mir and mir.group(1)} — transform only validated for rot0/no-mirror.")
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libname = module_lib.split(':')[-1]
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pins = {}
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for pm in re.finditer(r'\(pin\b.*?\(at' + S + r'([\d.-]+)' + S + r'([\d.-]+)' + S + r'[\d.-]+\).*?\(number' + S + r'"([^"]+)"', t, re.S):
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lx, ly, num = float(pm.group(1)), float(pm.group(2)), pm.group(3)
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pins.setdefault(num, (round(px + lx, 2), round(py - ly, 2)))
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return pins, unit
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def collect(t, pat):
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"""Return list of (start,end,coord,text) for top-level objects named `pat` token."""
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out = []
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for m in re.finditer(r'\(' + pat + r'\b', t):
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s = m.start(); e = paren_end(t, s); seg = t[s:e]
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at = re.search(r'\(at' + S + r'([\d.-]+)' + S + r'([\d.-]+)', seg)
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out.append((s, e, (fnum(at.group(1)), fnum(at.group(2))) if at else None, seg))
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return out
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def wire_pts(seg):
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return [(fnum(a), fnum(b)) for a, b in re.findall(r'\(xy' + S + r'([\d.-]+)' + S + r'([\d.-]+)\)', seg)]
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def lib_pins(t, lib_id):
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"""Local (lx,ly,angle) for every pin of a lib_symbol definition."""
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name = lib_id.split(':')[-1]
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lm = re.search(r'\(symbol' + S + r'"' + re.escape(lib_id) + r'"', t) or \
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re.search(r'\(symbol' + S + r'"' + re.escape(name) + r'"', t)
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if not lm: return []
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seg = t[lm.start():paren_end(t, lm.start())]
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return [(float(a), float(b), float(c)) for a, b, c in
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re.findall(r'\(pin\b.*?\(at' + S + r'([\d.-]+)' + S + r'([\d.-]+)' + S + r'([\d.-]+)\)', seg, re.S)]
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def placed_symbols(t):
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"""Yield dict per placed symbol: start,end,ref,lib,at(px,py,rot),mirror."""
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for m in re.finditer(r'\(symbol' + S + r'\(lib_id' + S + r'"([^"]+)"\)', t):
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s = m.start(); e = paren_end(t, s); seg = t[s:e]
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ref = re.search(r'\(property' + S + r'"Reference"' + S + r'"([^"]+)"', seg)
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at = re.search(r'\(at' + S + r'([\d.-]+)' + S + r'([\d.-]+)' + S + r'([\d.-]+)\)', seg)
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mir = re.search(r'\(mirror' + S + r'(\w+)\)', seg)
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yield dict(s=s, e=e, ref=ref.group(1) if ref else None, lib=m.group(1),
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at=(float(at.group(1)), float(at.group(2)), float(at.group(3))) if at else None,
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mirror=mir.group(1) if mir else None)
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def sym_pin_coords(t, sym):
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if not sym['at']: return []
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px, py, rot = sym['at']
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return [xform(px, py, rot, sym['mirror'], lx, ly) for lx, ly, _ in lib_pins(t, sym['lib'])]
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def drop_sheet_spans(t, fname):
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"""Remove an entire (sheet ...) block by its Sheetfile property, plus any
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(path ...) in (sheet_instances) referencing the sheet's UUID. Run on the parent
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(root) sheet. Returns list of (start,end) spans to delete."""
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spans = []
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for m in re.finditer(r'\(sheet\b', t):
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s = m.start(); e = paren_end(t, s); seg = t[s:e]
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sf = re.search(r'Sheetfile"' + S + r'"([^"]+)"', seg)
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if not sf or sf.group(1) != fname: continue
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spans.append((s, e))
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u = re.search(r'\(uuid' + S + r'"([0-9a-fA-F-]+)"', seg)
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if u:
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si = re.search(r'\(sheet_instances\b', t)
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if si:
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ss = si.start(); se = paren_end(t, ss)
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for pm in re.finditer(r'\(path' + S + r'"[^"]*' + re.escape(u.group(1)) + r'[^"]*"', t[ss:se]):
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ps = ss + pm.start(); spans.append((ps, paren_end(t, ps)))
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return spans
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def sheet_port_spans(t, names):
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"""On a ROOT sheet, find (pin "NAME" ...) hierarchical ports inside (sheet ...) blocks
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whose name is in `names`. Returns (pin spans to remove, their connection coords)."""
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spans, coords = [], set()
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for m in re.finditer(r'\(sheet\b', t):
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s = m.start(); e = paren_end(t, s)
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for pm in re.finditer(r'\(pin' + S + r'"([^"]+)"', t[s:e]):
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if pm.group(1) in names:
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ps = s + pm.start(); pe = paren_end(t, ps)
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at = re.search(r'\(at' + S + r'([\d.-]+)' + S + r'([\d.-]+)', t[ps:pe])
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spans.append((ps, pe))
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if at: coords.add((fnum(at.group(1)), fnum(at.group(2))))
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return spans, coords
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def main():
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ap = argparse.ArgumentParser()
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ap.add_argument('sheet')
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ap.add_argument('--symbols', default='')
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ap.add_argument('--nets', default='')
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ap.add_argument('--nc-pins', default='', help='module pin NUMBERS to no-connect (from analyzer regressions)')
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ap.add_argument('--sheet-ports', default='', help='hierarchical net names: remove matching sheet-symbol pins + connecting root wires (run on the ROOT sheet)')
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ap.add_argument('--drop-sheet', default='', help='Sheetfile name: remove the whole (sheet ...) block + its sheet_instances path (run on the ROOT/parent sheet)')
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ap.add_argument('--module-lib', default='CM5IO:ComputeModule5-CM5')
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ap.add_argument('--apply', action='store_true')
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a = ap.parse_args()
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drop_refs = set(filter(None, a.symbols.split(',')))
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net_globs = list(filter(None, a.nets.split(',')))
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nc_nums = list(filter(None, a.nc_pins.split(',')))
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port_names = set(filter(None, a.sheet_ports.split(',')))
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t = open(a.sheet).read()
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modpins, unit = module_pins_abs(t, a.module_lib)
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pin_at = {xy: n for n, xy in modpins.items()}
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nc_pins = [(n, modpins[n]) for n in nc_nums if n in modpins]
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missing_nc = [n for n in nc_nums if n not in modpins]
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if missing_nc: sys.exit(f"NC pins not found on module: {missing_nc}")
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# 1) symbols to remove + their abs pin coords (for stub cleanup)
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placed = list(placed_symbols(t))
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removed_syms = [sy for sy in placed if sy['ref'] in drop_refs]
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found_refs = {sy['ref'] for sy in removed_syms}
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sym_spans = [(sy['s'], sy['e']) for sy in removed_syms]
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removed_pin_coords = set()
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for sy in removed_syms:
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removed_pin_coords |= set(sym_pin_coords(t, sy))
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# 2) retired labels by glob — match ANY label type (local / hierarchical / global)
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labels = collect(t, 'label') + collect(t, 'hierarchical_label') + collect(t, 'global_label')
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retired_labels = [(s, e, c) for s, e, c, seg in labels
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for nm in [re.search(r'"([^"]+)"', seg).group(1)]
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if any(fnmatch.fnmatch(nm, g) for g in net_globs)]
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retired_coords = {c for _, _, c in retired_labels}
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# 3) anchor-aware wire removal via connected components.
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# A wire is removed only if its component (a) is orphaned by THIS edit (touches a
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# removed pin, retired label, or target NC pin) AND (b) reaches no KEPT anchor —
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# a kept non-power component pin or a kept label. Shared nets (e.g. a camera FFC's
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# I2C/power pins) stay anchored by the kept side, so they survive; pre-existing
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# floating wires aren't seeded, so they're untouched.
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wires = collect(t, 'wire')
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wpts = [(s, e, wire_pts(seg)) for s, e, _, seg in wires]
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parent = {}
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def find(x):
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parent.setdefault(x, x)
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root = x
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while parent[root] != root: root = parent[root]
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while parent[x] != root: parent[x], x = root, parent[x]
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return root
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def union(a, b): parent[find(a)] = find(b)
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for s, e, pts in wpts:
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for p in pts[1:]:
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union(pts[0], p)
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nc_coords = {xy for _, xy in nc_pins}
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kept_label_coords = {c for s, e, c, seg in labels
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if not any(fnmatch.fnmatch(re.search(r'"([^"]+)"', seg).group(1), g)
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for g in net_globs)}
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kept_pin_coords = set()
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for sy in placed:
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if sy['ref'] in drop_refs or sy['lib'].startswith('power:'): continue
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kept_pin_coords |= set(sym_pin_coords(t, sy))
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kept_pin_coords -= nc_coords # pins we are NC'ing are being disconnected
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anchors = kept_pin_coords | kept_label_coords
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# sheet-symbol hierarchical ports to drop (root sheet) + their connection coords
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port_spans, port_coords = sheet_port_spans(t, port_names) if port_names else ([], set())
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sheet_spans = drop_sheet_spans(t, a.drop_sheet) if a.drop_sheet else []
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seeds = set(removed_pin_coords) | set(retired_coords) | nc_coords | port_coords
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anchored_roots, seeded_roots = set(), set()
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for c in anchors:
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if c in parent: anchored_roots.add(find(c))
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for c in seeds:
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if c in parent: seeded_roots.add(find(c))
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removable_roots = seeded_roots - anchored_roots
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wire_remove = [(s, e, pts) for s, e, pts in wpts if find(pts[0]) in removable_roots]
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wire_remove_spans = {(s, e) for s, e, _ in wire_remove}
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freed = set(removed_pin_coords)
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for _, _, pts in wire_remove:
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freed |= set(pts)
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kept_wire_pts = set()
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for s, e, pts in wpts:
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if (s, e) not in wire_remove_spans:
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kept_wire_pts |= set(pts)
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flooded_wires = wire_remove # naming compat for the summary print
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stub_wires = []
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# 5) orphaned power flags (power:*): pin freed by my edit, no kept wire left on it
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power_spans = []
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for sy in placed:
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if sy['ref'] in drop_refs or not sy['lib'].startswith('power:'): continue
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pcs = sym_pin_coords(t, sy)
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if pcs and all(pc in freed and pc not in kept_wire_pts for pc in pcs):
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power_spans.append((sy['s'], sy['e']))
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# 6) dangling no_connects sitting on a removed symbol's pin
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dangling_nc = [(s, e) for s, e, c, _ in collect(t, 'no_connect') if c in removed_pin_coords]
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# 7) labels orphaned by my edit (any label type): coord freed, no kept wire left,
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# not already retired. Covers local (label), and cross-sheet (hierarchical_label /
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# global_label) that only fed a removed connector (e.g. a camera FFC's SCL0/CAM_GPIO).
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retired_label_spans = {(s, e) for s, e, _ in retired_labels}
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all_label_objs = collect(t, 'label') + collect(t, 'hierarchical_label') + collect(t, 'global_label')
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orphan_labels = [(s, e) for s, e, c, _ in all_label_objs
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if (s, e) not in retired_label_spans and c in freed and c not in kept_wire_pts]
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nc_pins = sorted(nc_pins, key=lambda kv: int(re.sub(r'\D', '', kv[0]) or 0))
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print(f"sheet: {a.sheet} (module unit {unit}, {len(modpins)} pins)")
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print(f"symbols to remove: {sorted(found_refs)} (requested {sorted(drop_refs)}; missing {sorted(drop_refs-found_refs)})")
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print(f"retired-net labels: {len(retired_labels)} | wires removed (anchor-aware): {len(wire_remove)}")
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print(f"orphaned power flags: {len(power_spans)} | dangling NC removed: {len(dangling_nc)} | orphaned labels: {len(orphan_labels)}")
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if port_names: print(f"sheet-symbol ports removed: {len(port_spans)} ({sorted(port_names)})")
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if a.drop_sheet: print(f"whole sheet dropped: {a.drop_sheet} ({len(sheet_spans)} block(s)/instance-path(s))")
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print(f"module pins to NC ({len(nc_pins)}): " + ", ".join(f"{n}@{xy}" for n, xy in nc_pins))
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# build new text: remove all spans, then append fresh no_connects on exposed module pins
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spans = sorted(set(sym_spans) | {(s, e) for s, e, _ in retired_labels}
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| wire_remove_spans | set(power_spans) | set(dangling_nc) | set(orphan_labels)
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| set(port_spans) | set(sheet_spans), key=lambda x: -x[0])
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nt = t
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for s, e in spans:
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p = s
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while p > 0 and nt[p-1] in '\t ': p -= 1
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if p > 0 and nt[p-1] == '\n': p -= 1
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nt = nt[:p] + nt[e:]
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# insert no_connect markers before the final closing paren of the sheet
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nc_block = "".join(
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f'\t(no_connect\n\t\t(at {xy[0]} {xy[1]})\n\t\t(uuid "{uuidlib.uuid5(uuidlib.NAMESPACE_DNS, a.sheet+n)}")\n\t)\n'
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for n, xy in nc_pins)
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last = nt.rstrip().rfind(')')
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nt = nt[:last] + nc_block + nt[last:]
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assert nt.count('(') == nt.count(')'), "UNBALANCED — aborting"
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if a.apply:
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open(a.sheet, 'w').write(nt)
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print(f"APPLIED. parens balanced ({nt.count('(')}). +{len(nc_pins)} no_connect, -{len(spans)} objects.")
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else:
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print(f"DRY RUN ok. parens would balance ({nt.count('(')}). Re-run with --apply to write.")
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if __name__ == '__main__':
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main()
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