rpicarrierboard

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Author	SHA1	Message	Date
noise	13496b302c	Power stage 4: TPS54202 15V->+3V3_AUX 1A quiet-rail buck (power sheet complete) - TPS54202 SOT-23-6 sync, fixed 500kHz; custom symbol CM5IO:TPS54202 (KiCad lib symbol extends TPS54302 with no own pins, cannot embed standalone) - Abs-max gate: VIN 30V vs SMBJ18A clamp <=29.2V at rated surge (0.8V margin, transient-only) - documented, passed - FB 100k/22.1k + 56pF Cff per TI 3.3V table -> 3.29V (SPICE: vfb 0.597V, inrush settles 3.315V); L 10uH, Cout 2x22uF/16V - EN abs-max 7V -> UVLO divider 866k/110k from VIN_PROT (start 10.13V / stop 8.61V, EN ~1.9V at 15V); no direct VIN tie - Renamed input cap C_IN33A -> C_IN33Aa: SPICE names are case-insensitive and collided with stage-3 C_IN33a, silently skipping the VIN_PROT decoupling sim - Verify: ERC 133->133 zero new; analyzer +65/-0 zero regressions; SPICE 23 pass / 2 benign warn / 0 fail / 0 skip Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>	2026-07-02 07:03:31 -04:00
noise	fd627f512b	Power stage 2: LM61460-Q1 15V->+5v 5A sync buck (SPICE-verified 5.02V) Second power stage. U_BUCK5 = LM61460-Q1 (6A, 42V abs-max synchronous). No KiCad symbol existed, so built one from the TI datasheet (SNVSB70F: 14-pin HTSSOP-1EP + EP, VREF=1.0V) and added it to the project library carrier/CM5IO.kicad_sym as CM5IO:LM61460-Q1. - FB divider R_FBT5 40.2k / R_FBB5 10.0k -> 5.02V (SPICE-confirmed vfb=1.0V=VREF at 5.02V); L5 4.7uH, Cout 2x47u/16V, Cin 2x10u/50V, Cboot 100n+Rboot, RT 31.6k (~400kHz), BIAS->+5v, EN->VIN_PROT - +5v pre-exists in the carrier as a hierarchical net -> exposed via a hierarchical label + a +5v sheet pin on the Power symbol, tied into the root +5v net (a global label would trip same_local_global_label). Netlist confirms the buck now sources Module1 + GPIO headers + USB. - FB pin typed passive (high-Z sense) to clear an analyzer no_driver - build_power.py: register_lm61460(), Device:L, HIER_NETS/emit_hlabel Verify: ERC 133->133 (zero new); analyzer +32 added, 0 regressions; SPICE 12/13 pass, 0 fail (1 benign warn: L5/Cboot mis-grouped as LC). Confirm vs datasheet: RT freq, L saturation >=7A, EP=pad15, EN UVLO. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>	2026-07-01 18:31:26 -04:00
noise	6082613e88	many eda additions	2026-06-29 16:31:02 -04:00

Author

SHA1

Message

Date

noise

13496b302c

Power stage 4: TPS54202 15V->+3V3_AUX 1A quiet-rail buck (power sheet complete)

- TPS54202 SOT-23-6 sync, fixed 500kHz; custom symbol CM5IO:TPS54202 (KiCad
  lib symbol extends TPS54302 with no own pins, cannot embed standalone)
- Abs-max gate: VIN 30V vs SMBJ18A clamp <=29.2V at rated surge (0.8V margin,
  transient-only) - documented, passed
- FB 100k/22.1k + 56pF Cff per TI 3.3V table -> 3.29V (SPICE: vfb 0.597V,
  inrush settles 3.315V); L 10uH, Cout 2x22uF/16V
- EN abs-max 7V -> UVLO divider 866k/110k from VIN_PROT (start 10.13V /
  stop 8.61V, EN ~1.9V at 15V); no direct VIN tie
- Renamed input cap C_IN33A -> C_IN33Aa: SPICE names are case-insensitive and
  collided with stage-3 C_IN33a, silently skipping the VIN_PROT decoupling sim
- Verify: ERC 133->133 zero new; analyzer +65/-0 zero regressions;
  SPICE 23 pass / 2 benign warn / 0 fail / 0 skip

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

2026-07-02 07:03:31 -04:00

noise

fd627f512b

Power stage 2: LM61460-Q1 15V->+5v 5A sync buck (SPICE-verified 5.02V)

Second power stage. U_BUCK5 = LM61460-Q1 (6A, 42V abs-max synchronous).
No KiCad symbol existed, so built one from the TI datasheet (SNVSB70F:
14-pin HTSSOP-1EP + EP, VREF=1.0V) and added it to the project library
carrier/CM5IO.kicad_sym as CM5IO:LM61460-Q1.

- FB divider R_FBT5 40.2k / R_FBB5 10.0k -> 5.02V (SPICE-confirmed
  vfb=1.0V=VREF at 5.02V); L5 4.7uH, Cout 2x47u/16V, Cin 2x10u/50V,
  Cboot 100n+Rboot, RT 31.6k (~400kHz), BIAS->+5v, EN->VIN_PROT
- +5v pre-exists in the carrier as a hierarchical net -> exposed via a
  hierarchical label + a +5v sheet pin on the Power symbol, tied into the
  root +5v net (a global label would trip same_local_global_label).
  Netlist confirms the buck now sources Module1 + GPIO headers + USB.
- FB pin typed passive (high-Z sense) to clear an analyzer no_driver
- build_power.py: register_lm61460(), Device:L, HIER_NETS/emit_hlabel

Verify: ERC 133->133 (zero new); analyzer +32 added, 0 regressions;
SPICE 12/13 pass, 0 fail (1 benign warn: L5/Cboot mis-grouped as LC).

Confirm vs datasheet: RT freq, L saturation >=7A, EP=pad15, EN UVLO.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-01 18:31:26 -04:00

noise

6082613e88

many eda additions

2026-06-29 16:31:02 -04:00

3 Commits