First stage of the power tree. New carrier/Power.kicad_sch (generated by
tools/build_power.py): J_PWR 15V inlet -> D_REV LM74700-Q1 ideal-diode
controller + Q_REV N-FET (reverse-polarity / reverse-current) -> VIN_PROT,
with SMBJ18A input TVS and 100uF/25V || 10uF/50V bulk + VCAP cap.
Part-selection note: the spec's buck candidates miss its own >=20V Vin rule
(TPS54424=17V, TPS54560=async); the 3 sync bucks (stages 2-4) will use
>=30V synchronous parts, datasheet-verified, feeding +5V/+3V3_RF/+3V3_AUX.
tools/build_power.py generalizes the build_ekey approach: generic place()
attaches a net label / GND symbol per pin (by-name connectivity, grid-snapped);
PWR_FLAGs co-located on real pin coords.
Verify: ERC 133->133 (zero new); analyzer +16 added, 0 regressions; netlist
confirms the ideal-diode topology (+15V_IN/VIN_PROT/GATE_REV/VCAP_REV/GND).
Confirm vs LM74700-Q1 datasheet: C_VCAP value, EN tie, FET Vds/SOA, gate R.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Drops the unused M.2 M-key/NVMe block — design is 1x M.2 E-key (Wi-Fi)
only, since the CM5 exposes a single PCIe x1 lane (datasheet SC1466),
reserved for the E-key. The 10 freed PCIE_* lanes are NC on Module1
unit 2, to be rewired to a fresh E-key sheet in the add phase.
- CM5_HighSpeed: retire PCIE_* labels/wires, NC pins 102,104,106,109,
110,112,116,118,122,124
- root CM5IO: drop whole PCIe-M2 (sheet) block; strip dangling PCIE_*
pins off the kept CM5_HighSpeed sheet symbol
- delete carrier/PCIe-M2.kicad_sch; clean .kicad_pro sheets array + ERC
exclusion
- retire_block.py: add --drop-sheet FILE (remove whole (sheet) block +
sheet_instances path)
- analysis/baseline/carrier_stripped.json: new add-phase diff anchor
Verify: ERC 136->133 (zero new violation types); analyzer diff +0/~0
(cumulative -41 removed vs original ref); netlist confirms +5v/+3.3v/
GND/+1.8v intact (U8's M2_3v3 was a local rail, not board +3.3v).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
