- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
SPICE 17 pass / 2 benign warn / 0 fail
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Second power stage. U_BUCK5 = LM61460-Q1 (6A, 42V abs-max synchronous).
No KiCad symbol existed, so built one from the TI datasheet (SNVSB70F:
14-pin HTSSOP-1EP + EP, VREF=1.0V) and added it to the project library
carrier/CM5IO.kicad_sym as CM5IO:LM61460-Q1.
- FB divider R_FBT5 40.2k / R_FBB5 10.0k -> 5.02V (SPICE-confirmed
vfb=1.0V=VREF at 5.02V); L5 4.7uH, Cout 2x47u/16V, Cin 2x10u/50V,
Cboot 100n+Rboot, RT 31.6k (~400kHz), BIAS->+5v, EN->VIN_PROT
- +5v pre-exists in the carrier as a hierarchical net -> exposed via a
hierarchical label + a +5v sheet pin on the Power symbol, tied into the
root +5v net (a global label would trip same_local_global_label).
Netlist confirms the buck now sources Module1 + GPIO headers + USB.
- FB pin typed passive (high-Z sense) to clear an analyzer no_driver
- build_power.py: register_lm61460(), Device:L, HIER_NETS/emit_hlabel
Verify: ERC 133->133 (zero new); analyzer +32 added, 0 regressions;
SPICE 12/13 pass, 0 fail (1 benign warn: L5/Cboot mis-grouped as LC).
Confirm vs datasheet: RT freq, L saturation >=7A, EP=pad15, EN UVLO.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
First stage of the power tree. New carrier/Power.kicad_sch (generated by
tools/build_power.py): J_PWR 15V inlet -> D_REV LM74700-Q1 ideal-diode
controller + Q_REV N-FET (reverse-polarity / reverse-current) -> VIN_PROT,
with SMBJ18A input TVS and 100uF/25V || 10uF/50V bulk + VCAP cap.
Part-selection note: the spec's buck candidates miss its own >=20V Vin rule
(TPS54424=17V, TPS54560=async); the 3 sync bucks (stages 2-4) will use
>=30V synchronous parts, datasheet-verified, feeding +5V/+3V3_RF/+3V3_AUX.
tools/build_power.py generalizes the build_ekey approach: generic place()
attaches a net label / GND symbol per pin (by-name connectivity, grid-snapped);
PWR_FLAGs co-located on real pin coords.
Verify: ERC 133->133 (zero new); analyzer +16 added, 0 regressions; netlist
confirms the ideal-diode topology (+15V_IN/VIN_PROT/GATE_REV/VCAP_REV/GND).
Confirm vs LM74700-Q1 datasheet: C_VCAP value, EN tie, FET Vds/SOA, gate R.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
