rpicarrierboard

noisedestroyers/rpicarrierboard

Fork 0

Commit Graph

Author	SHA1	Message	Date
noise	261bf48bb4	Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN - Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V, inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz) - BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below) - EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail stays off until CM5 asserts it; netlist-verified 3-node net - Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now the sole +3V3_RF driver - Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions; SPICE 17 pass / 2 benign warn / 0 fail Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>	2026-07-01 22:11:24 -04:00
noise	18ef98a88e	Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E (fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915 Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the PCIe-M2 drop (design confirmed E-key-only, no M-key SSD). - PCIe link-0 wired to the 9 freed CM5 pins via global labels (TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1 - +3V3_RF (pins 2/4/72/74) + 10uF\|\|2x0.1uF decoupling + temp PWR_FLAG - W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.) - RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec); corrected Pinout_BOM, dropped C_PCIE - CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels (106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN) - root + .kicad_pro: registered the M2_Ekey sub-sheet - tools/build_ekey.py: new generator (place connector + auto-NC unused pins + by-name labels; grid-snap; cross-connector ERC pin retyping) Verify: ERC 133->133 (zero new violations); analyzer diff +7 added, 0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1. Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once the +3V3_RF buck drives the rail. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>	2026-06-30 14:58:09 -04:00

Author

SHA1

Message

Date

noise

261bf48bb4

Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN

- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
  inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
  CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
  stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
  the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
  SPICE 17 pass / 2 benign warn / 0 fail

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

2026-07-01 22:11:24 -04:00

noise

18ef98a88e

Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes

First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).

- PCIe link-0 wired to the 9 freed CM5 pins via global labels
  (TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
  corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
  (106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
  pins + by-name labels; grid-snap; cross-connector ERC pin retyping)

Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.

Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-06-30 14:58:09 -04:00

2 Commits