Power stage 2: LM61460-Q1 15V->+5v 5A sync buck (SPICE-verified 5.02V)

Second power stage. U_BUCK5 = LM61460-Q1 (6A, 42V abs-max synchronous).
No KiCad symbol existed, so built one from the TI datasheet (SNVSB70F:
14-pin HTSSOP-1EP + EP, VREF=1.0V) and added it to the project library
carrier/CM5IO.kicad_sym as CM5IO:LM61460-Q1.

- FB divider R_FBT5 40.2k / R_FBB5 10.0k -> 5.02V (SPICE-confirmed
  vfb=1.0V=VREF at 5.02V); L5 4.7uH, Cout 2x47u/16V, Cin 2x10u/50V,
  Cboot 100n+Rboot, RT 31.6k (~400kHz), BIAS->+5v, EN->VIN_PROT
- +5v pre-exists in the carrier as a hierarchical net -> exposed via a
  hierarchical label + a +5v sheet pin on the Power symbol, tied into the
  root +5v net (a global label would trip same_local_global_label).
  Netlist confirms the buck now sources Module1 + GPIO headers + USB.
- FB pin typed passive (high-Z sense) to clear an analyzer no_driver
- build_power.py: register_lm61460(), Device:L, HIER_NETS/emit_hlabel

Verify: ERC 133->133 (zero new); analyzer +32 added, 0 regressions;
SPICE 12/13 pass, 0 fail (1 benign warn: L5/Cboot mis-grouped as LC).

Confirm vs datasheet: RT freq, L saturation >=7A, EP=pad15, EN UVLO.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

carrier/CM5IO.kicad_sch

@@ -3477,8 +3477,18 @@
 		(uuid "9c7ccf72-dd3e-5ed3-bb43-2939833eb069")
 		(property "Sheetname" "Power" (at 205 56.18 0) (effects (font (size 1.27 1.27)) (justify left bottom)))
 		(property "Sheetfile" "Power.kicad_sch" (at 205 57.45 0) (effects (font (size 1.27 1.27)) (justify left top)))
+		(pin "+5v" passive
+			(at 205 66 180)
+			(effects (font (size 1.27 1.27)) (justify right))
+			(uuid "6a42935f-df5f-5ead-a94c-89074919a7c3")
+		)
 		(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55" (page "5"))))
 	)
+	(label "+5v"
+		(at 205 66 0)
+		(effects (font (size 1.27 1.27)) (justify left))
+		(uuid "f1109a7e-4bfb-54f4-a32e-e6719bad4ba8")
+	)
 	(sheet_instances
 		(path "/"
 			(page "1")