docs: add session-handoff RESUME header to PORT_STATUS

Explicit resume pointer for a fresh session: current state (HEAD, sheets,
ERC=133 baseline), the exact next action (Power Stage 3 U_BUCK33R +3V3_RF
with FB divider + E-key PWR_FLAG removal + PCIE_PWR_EN/EN wiring), and the
build/verify commands + gotchas.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

PORT_STATUS.md

@@ -4,6 +4,40 @@
 > `.claude/skills/kicad-port/SKILL.md` (the mandatory workflow/verify-loop), then
 > `CM5_Carrier_Design.md` (frozen rev-A spec).
 
+## ▶ RESUME HERE (session handoff, 2026-07-01)
+
+**State:** branch `port/strip-phase`, HEAD `fd627f5`, working tree clean (only unrelated
+`refs/.history` submodule blip). Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`, `CM5_HighSpeed`
+(reference, stripped), `M2_Ekey` (E-key, done), `Power` (stages 1–2 done). Baseline anchor:
+`analysis/baseline/carrier_stripped.json`.
+
+**Done:** strip phase (microSD/HDMI/MIPI/PCIe-M2); M.2 E-key sheet (PCIe ×1 to CM5); Power
+stage 1 (LM74700 ideal-diode input protection → `VIN_PROT`); Power stage 2 (LM61460-Q1
+15→`+5v` 5 A sync buck, SPICE-verified 5.02 V). Current whole-design **ERC = 133** (all
+pre-existing types; a good edit adds **zero new**).
+
+**NEXT ACTION → Power Stage 3: `U_BUCK33R` 15→`+3V3_RF` 4 A.** Edit `tools/build_power.py`,
+append a Stage-3 block (copy the Stage-2 pattern): reuse the `CM5IO:LM61460-Q1` symbol; FB
+divider for 3.3 V → ratio 2.3 → `R_FBT 23.2k / R_FBB 10.0k` (SPICE-verify vfb=1.0 V @ 3.32 V);
+same L/Cin/Cout/boot/RT support. Then **(a)** delete the E-key temp `PWR_FLAG` on `+3V3_RF`
+(`#FLG33RF` in `carrier/M2_Ekey.kicad_sch` via build_ekey — the buck is the real driver now),
+and **(b)** wire the buck `EN` ← CM5 `PCIE_PWR_EN` (Module1 pin 106, currently NC on
+`CM5_HighSpeed`) for SW radio-power control. `+3V3_RF` is a NEW net → keep it a **global** label
+(no `same_local_global_label` risk, unlike `+5v`). Then Stage 4 (`+3V3_AUX`, TPS54202 28 V),
+then the GPS + PPS sheet.
+
+**How to build/verify (every change):**
+- Sheets are generated wholesale — edit `tools/build_ekey.py` / `tools/build_power.py`, then
+  `python3 tools/build_power.py --apply`. Custom IC symbols go in `carrier/CM5IO.kicad_sym`
+  (bare name) AND embed in the sheet as `CM5IO:<name>` — else ERC `lib_symbol_issues`.
+- Verify loop (judge by the **integrated root** run, not standalone sub-sheets):
+  `kicad-cli sch erc --format json -o /tmp/e.json carrier/CM5IO.kicad_sch` (track delta vs 133,
+  zero new types) → `analyze_schematic.py carrier/CM5IO.kicad_sch` + `diff_analysis.py
+  analysis/baseline/carrier_stripped.json …` (zero regressions) → for bucks, `simulate_subcircuits.py`.
+- Gotchas (full list in memory `port-progress`): grid-snap all coords to 1.27 mm or labels don't
+  bind; PWR_FLAG/GND must sit on a real pin coord; pre-existing `+5v` is hierarchical (not global);
+  type feedback pins `passive`; connector/module pin types may need remodeling for cross-part ERC.
+
 ## What this repo is
 
 Two intertwined goals: