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Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN

Browse Source 
- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
  inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
  CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
  stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
  the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
  SPICE 17 pass / 2 benign warn / 0 fail

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
noise
2026-07-01 22:11:24 -04:00
parent d72f3a4bd8
commit 261bf48bb4
6 changed files with 594 additions and 41 deletions
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31
PORT_STATUS.md
View File

@@ -6,25 +6,23 @@
## ▶ RESUME HERE (session handoff, 2026-07-01)
**State:** branch `port/strip-phase`, HEAD `fd627f5`, working tree clean (only unrelated
`refs/.history` submodule blip). Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`, `CM5_HighSpeed`
(reference, stripped), `M2_Ekey` (E-key, done), `Power` (stages 1–2 done). Baseline anchor:
`analysis/baseline/carrier_stripped.json`.
**State:** branch `port/strip-phase`. Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`,
`CM5_HighSpeed` (reference, stripped), `M2_Ekey` (E-key, done), `Power` (stages 1–3 done).
Baseline anchor: `analysis/baseline/carrier_stripped.json`.
**Done:** strip phase (microSD/HDMI/MIPI/PCIe-M2); M.2 E-key sheet (PCIe ×1 to CM5); Power
stage 1 (LM74700 ideal-diode input protection → `VIN_PROT`); Power stage 2 (LM61460-Q1
15→`+5v` 5 A sync buck, SPICE-verified 5.02 V). Current whole-design **ERC = 133** (all
pre-existing types; a good edit adds **zero new**).
15→`+5v` 5 A sync buck, SPICE-verified 5.02 V); Power stage 3 (LM61460-Q1 15→`+3V3_RF` 4 A,
SPICE-verified 3.32 V; EN ← CM5 `PCIE_PWR_EN`/106 + 100k pull-down like reference R14; E-key
temp PWR_FLAG removed — buck is the sole `+3V3_RF` driver). Current whole-design **ERC = 133**
(all pre-existing types; a good edit adds **zero new**).
**NEXT ACTION → Power Stage 3: `U_BUCK33R` 15→`+3V3_RF` 4 A.** Edit `tools/build_power.py`,
append a Stage-3 block (copy the Stage-2 pattern): reuse the `CM5IO:LM61460-Q1` symbol; FB
divider for 3.3 V → ratio 2.3 → `R_FBT 23.2k / R_FBB 10.0k` (SPICE-verify vfb=1.0 V @ 3.32 V);
same L/Cin/Cout/boot/RT support. Then **(a)** delete the E-key temp `PWR_FLAG` on `+3V3_RF`
(`#FLG33RF` in `carrier/M2_Ekey.kicad_sch` via build_ekey — the buck is the real driver now),
and **(b)** wire the buck `EN` ← CM5 `PCIE_PWR_EN` (Module1 pin 106, currently NC on
`CM5_HighSpeed`) for SW radio-power control. `+3V3_RF` is a NEW net → keep it a **global** label
(no `same_local_global_label` risk, unlike `+5v`). Then Stage 4 (`+3V3_AUX`, TPS54202 28 V),
then the GPS + PPS sheet.
**NEXT ACTION → Power Stage 4: `U_BUCK33A` 15→`+3V3_AUX` ~1 A.** Candidate part TPS54202
(28 V sync) — datasheet-verify first (KiCad has `Regulator_Switching:TPS54202DDC`). One check
that MUST pass: the SMBJ18A clamp (~29 V at rated Ipp) vs the part's VIN abs-max — if the
datasheet says <30 V abs-max, pick a 36 V-class sync part instead (LMR51430/TPS54360-class)
or justify why the surge case is acceptable. FB divider per that part's VREF; SPICE-verify.
`+3V3_AUX` is a NEW net → **global** label. Then the GPS + PPS sheet, then power-budget review.
**How to build/verify (every change):**
- Sheets are generated wholesale — edit `tools/build_ekey.py` / `tools/build_power.py`, then
@@ -134,7 +132,8 @@ Notes that bit us (don't re-learn the hard way):
4. **Power sheet** (`carrier/Power.kicad_sch`, generated by `tools/build_power.py`) — staged, **sync + datasheet-built parts** (user choice). **Spec rating fix:** the spec's buck candidates miss its own ≥20V-Vin rule (TPS54424=17V, TPS54560=async) — selecting synchronous ≥30V parts instead (LM61460-class 6A for +5V & +3V3_RF/4A; TPS54202 28V for +3V3_AUX), each verified vs datasheet before commit.
- **Stage 1 — input protection ✅ DONE.** J_PWR(15V) → D_REV `LM74700-Q1` ideal-diode + Q_REV N-FET (reverse-polarity/-current) → `VIN_PROT`; `SMBJ18A` TVS + 100µF/25V ∥ 10µF/50V bulk; C_VCAP charge-pump cap. Netlist-verified topology; ERC 133→133 (zero new); analyzer 0 regressions. **Confirm vs LM74700-Q1 datasheet:** C_VCAP value, EN-to-+15V_IN, FET pick (Vds≥30V, SOA/inrush) + optional gate R.
- **Stage 2 — U_BUCK5 15→`+5v` 5A ✅ DONE.** `LM61460-Q1` (6A, 42V absmax sync; **custom symbol built from the datasheet** → `carrier/CM5IO.kicad_sym` as `CM5IO:LM61460-Q1`, fp `Package_SO:Texas_HTSSOP-14-1EP…ThermalVias`). VREF=1.0V → FB divider R_FBT5 40.2k / R_FBB5 10.0k = **5.02V (SPICE-confirmed vfb=1.0V)**. L5 4.7µH, Cout 2×47µF/16V, Cin 2×10µF/50V, Cboot 100n+Rboot 4.7Ω, RT 31.6k(~400kHz), BIAS→+5v, EN→VIN_PROT, PGOOD 100k→+5v. **`+5v` kept HIERARCHICAL** (pre-existing carrier net; global would collide `same_local_global_label`) — Power sheet exposes a `+5v` sheet pin, tied into the root `+5v` net; netlist-verified it drives Module1 + GPIO + USB. ERC 133→133 (zero new); analyzer +32 added **0 regressions**; SPICE 12/13 pass, 1 benign warn (L5/Cboot mis-detected as LC filter). **Confirm vs datasheet:** RT freq, L sat ≥7A, EP=pad15, optional EN UVLO divider.
- **Stage 3** U_BUCK33R 15→3.3V 4A → `+3V3_RF` (then REMOVE the E-key temp PWR_FLAG; wire buck EN ← CM5 `PCIE_PWR_EN`/106). **Stage 4** U_BUCK33A 15→3.3V 1A → `+3V3_AUX`. SPICE-validate each feedback divider.
- **Stage 3 — U_BUCK33R 15→`+3V3_RF` 4A ✅ DONE.** Second `LM61460-Q1` (shared BOM with stage 2: L 4.7µH/7A ripple ~1.3A=33%, Cin 2×10µ/50V, Cout 2×47µ/16V, RT 31.6k ~420kHz, Cboot 100n+Rboot 4.7). FB divider R_FBT33 23.2k / R_FBB33 10.0k = **3.32V (SPICE: vfb 0.994V, inrush settles 3.32V)**. BIAS→`+3V3_RF` (datasheet: valid ≥3.1V, auto-falls back to VIN below). **EN ← CM5 `PCIE_PWR_EN`** (Module1 pin 106: NC swapped for a global label on `CM5_HighSpeed`) + **R_EN33 100k pull-down** (mirrors reference R14 — netlist-verified `Module1.106 + U_BUCK33R.7 + R_EN33.1`) so the Wi-Fi rail is OFF until the CM5 asserts it. **E-key temp `#FLG33RF` PWR_FLAG removed** (build_ekey); the buck's PWR_FLAG on L33.2 is now the sole `+3V3_RF` driver — netlist shows buck + all 4 J_E power pins + pull-ups + decoupling on one net. Verify: ERC 133→133 zero new; analyzer +49 added **0 regressions**; SPICE 17 pass / 2 benign warn (the L/C_BOOT "LC filter" mis-detect, once per buck) / 0 fail. (Note: `kicad-cli` netlist export prints a pre-existing "annotation errors" warning — un-numbered generated refdeses like `J_E`/`J_PWR`; present at fd627f5 too, cosmetic.)
- **Stage 4** U_BUCK33A 15→3.3V ~1A → `+3V3_AUX`. SPICE-validate the feedback divider (see NEXT ACTION above for the part-selection gate).
5. **GPS + PPS distribution**: GPS connector (PPS+UART+3V3+GND); PPS → TVS → Schmitt (LVC1G17) →
fan-out: CM5 `Ethernet_SYNC_OUT` (J2 pin-6 net, 3.3V, no translator) + 2 header taps. SPICE/timing check.

8
carrier/CM5_HighSpeed.kicad_sch
View File

@@ -12684,9 +12684,11 @@
(at 38.1 144.78)
(uuid "3e94757c-62b4-5b7d-9eb9-0bce1d18da64")
)
(no_connect
(at 38.1 30.48)
(uuid "22043a85-7370-5a2b-9195-7034c3f95e65")
(global_label "PCIE_PWR_EN"
(shape input)
(at 38.1 30.48 180)
(effects (font (size 1.27 1.27)) (justify right))
(uuid "ec1f5dd4-69da-5539-9a4f-28c69e37960f")
)
(global_label "PCIE_nCLKREQ"
(shape input)

13
carrier/M2_Ekey.kicad_sch
View File

@@ -2298,19 +2298,6 @@
(pin "1" (uuid "4b6d8ed9-33cb-576b-b25a-4d7450c86b69"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#PWRC_E3g") (unit 1))))
)
(symbol
(lib_id "power:PWR_FLAG")
(at 214.63 106.68 0)
(unit 1)
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
(uuid "57cb1e76-9a59-5707-bae8-cb2acbf83bcd")
(property "Reference" "#FLG33RF" (at 214.63 103.68 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Value" "PWR_FLAG" (at 214.63 104.68 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 214.63 106.68 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Datasheet" "" (at 214.63 106.68 0) (effects (font (size 1.27 1.27)) (hide yes)))
(pin "1" (uuid "63df115b-4a9f-5dd3-b381-99eea593a368"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/c57f5f03-e2c5-5c1b-ba90-8072a2a088a0" (reference "#FLG33RF") (unit 1))))
)
(sheet_instances
(path "/"
(page "4")

545
carrier/Power.kicad_sch
View File

@@ -2558,6 +2558,551 @@
(pin "1" (uuid "27e0e6b7-4281-5c4d-b9d6-26200e20eae9"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/9c7ccf72-dd3e-5ed3-bb43-2939833eb069" (reference "#FLGP5V") (unit 1))))
)
(symbol
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(at 229.87 149.86 0)
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(uuid "046070ba-66fb-59cc-98a8-53761c19a7e1")
(property "Reference" "U_BUCK33R" (at 232.41 148.86 0) (effects (font (size 1.27 1.27)) (justify left)))
(property "Value" "LM61460-Q1" (at 232.41 150.86 0) (effects (font (size 1.27 1.27)) (justify left)))
(property "Footprint" "Package_SO:Texas_HTSSOP-14-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3.155x3.255mm_ThermalVias" (at 229.87 149.86 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Datasheet" "" (at 229.87 149.86 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Description" "" (at 229.87 149.86 0) (effects (font (size 1.27 1.27)) (hide yes)))
(pin "1" (uuid "da577313-4e1a-5f91-b7d8-960d0fb4836c"))
(pin "2" (uuid "249cfe65-2f70-5264-9499-3fe669a6c397"))
(pin "3" (uuid "22366cf7-2a57-5569-81ad-575461026da7"))
(pin "4" (uuid "f1fb0dfb-2df7-5bec-8838-65e99bc490cf"))
(pin "5" (uuid "716461bc-0a8d-53e3-9ace-71cb12ba83c7"))
(pin "6" (uuid "e269d70e-36d7-59bc-a043-b45077f572bf"))
(pin "7" (uuid "193ab7bf-5ef1-572e-bbf2-3b6404692c97"))
(pin "8" (uuid "1d89675f-9645-5665-a653-b5f422027dd2"))
(pin "9" (uuid "d2fe1512-c325-591b-bda8-e94c89b51063"))
(pin "10" (uuid "8c4ef216-239c-5b67-b0d9-cb0c26426dd3"))
(pin "11" (uuid "34382b88-a790-587f-b390-6555f56d93c0"))
(pin "12" (uuid "c4877149-42e0-5804-aa78-a0be3c4cb486"))
(pin "13" (uuid "a2b26205-9cce-59bf-80b5-4955f0a1a421"))
(pin "14" (uuid "36ab0c65-d586-5540-b3d0-5b3ae11a7ac9"))
(pin "15" (uuid "8b01e30f-5e3f-58b5-92e1-510de24ac156"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/9c7ccf72-dd3e-5ed3-bb43-2939833eb069" (reference "U_BUCK33R") (unit 1))))
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(uuid "df0ee602-1c0a-5b3b-92be-6469e4bef8ce")
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(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/9c7ccf72-dd3e-5ed3-bb43-2939833eb069" (reference "#PWRC_OUT33a2") (unit 1))))
)
(symbol
(lib_id "Device:C")
(at 245.11 165.1 0)
(unit 1)
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
(uuid "445475c3-e364-5c31-ad95-90047644c5b9")
(property "Reference" "C_OUT33b" (at 247.65 164.1 0) (effects (font (size 1.27 1.27)) (justify left)))
(property "Value" "47u/16V" (at 247.65 166.1 0) (effects (font (size 1.27 1.27)) (justify left)))
(property "Footprint" "Capacitor_SMD:C_1210_3225Metric" (at 245.11 165.1 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Datasheet" "" (at 245.11 165.1 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Description" "" (at 245.11 165.1 0) (effects (font (size 1.27 1.27)) (hide yes)))
(pin "1" (uuid "7aa57847-73b5-5c05-b767-bb62ce89d618"))
(pin "2" (uuid "69d9a762-5886-5ab1-b7ed-06843f7d57e4"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/9c7ccf72-dd3e-5ed3-bb43-2939833eb069" (reference "C_OUT33b") (unit 1))))
)
(global_label "+3V3_RF"
(shape input)
(at 245.11 161.29 0)
(effects (font (size 1.27 1.27)) (justify left))
(uuid "9433b865-be13-549a-bfd7-1a6d376c760f")
)
(symbol
(lib_id "power:GND")
(at 245.11 168.91 0)
(unit 1)
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
(uuid "af36ee75-239f-5915-a82d-a734af60520e")
(property "Reference" "#PWRC_OUT33b2" (at 245.11 171.91 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Value" "GND" (at 245.11 170.91 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 245.11 168.91 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Datasheet" "" (at 245.11 168.91 0) (effects (font (size 1.27 1.27)) (hide yes)))
(pin "1" (uuid "a80d941d-9847-5500-bc99-f819ef1b4111"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/9c7ccf72-dd3e-5ed3-bb43-2939833eb069" (reference "#PWRC_OUT33b2") (unit 1))))
)
(symbol
(lib_id "power:PWR_FLAG")
(at 270.51 142.24 0)
(unit 1)
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no)
(uuid "1303478c-fb2d-5112-9517-fee0895b93f1")
(property "Reference" "#FLGP33R" (at 270.51 139.24 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Value" "PWR_FLAG" (at 270.51 140.24 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 270.51 142.24 0) (effects (font (size 1.27 1.27)) (hide yes)))
(property "Datasheet" "" (at 270.51 142.24 0) (effects (font (size 1.27 1.27)) (hide yes)))
(pin "1" (uuid "0e8e4211-812c-5f32-b112-8a33a94d41da"))
(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/9c7ccf72-dd3e-5ed3-bb43-2939833eb069" (reference "#FLGP33R") (unit 1))))
)
(sheet_instances
(path "/"
(page "5")

10
tools/build_ekey.py
View File

@@ -211,19 +211,13 @@ place_rc("Device:R", "R_E1", "10k", "Resistor_SMD:R_0402_1005Metric", g(215.0),
place_rc("Device:R", "R_E2", "10k", "Resistor_SMD:R_0402_1005Metric", g(225.0), g(80.0), loc_label, "WIFI_DISABLE2#", "+3V3_RF")
# decoupling caps: pin1 -> +3V3_RF ; pin2 -> GND
c_e1_pin1 = None
for i, (ref, val) in enumerate([("C_E1", "10u"), ("C_E2", "100n"), ("C_E3", "100n")]):
cx = g(215.0 + i * 7.62); cy = g(110.0)
body.append(passive("Device:C", ref, val, "Capacitor_SMD:C_0402_1005Metric", cx, cy, ref))
p1 = (cx, round(cy - 3.81, 2))
body.append(glob_label("+3V3_RF", p1[0], p1[1], 90)) # pin1
body.append(glob_label("+3V3_RF", cx, round(cy - 3.81, 2), 90)) # pin1
body.append(gnd_sym(cx, round(cy + 3.81, 2), ref + "g")) # pin2 -> GND symbol
if ref == "C_E1": c_e1_pin1 = p1
# one PWR_FLAG to drive +3V3_RF until the power-sheet buck exists.
# Co-locate its pin directly on an existing +3V3_RF node (C_E1 pin1) so it binds.
# REMOVE this flag once the power sheet's buck drives +3V3_RF (else dual-driver ERC).
body.append(pwr_flag(c_e1_pin1[0], c_e1_pin1[1], "33RF"))
# +3V3_RF is driven by the Power sheet's U_BUCK33R (PWR_FLAG lives there).
# ---- file scaffold -----------------------------------------------------------------
libsyms = "\n".join([DEV_R, DEV_C, PWR_GND, pflag, sock])

28
tools/build_power.py
View File

@@ -101,7 +101,7 @@ register_lm61460()
# +5v pre-exists in the carrier as a HIERARCHICAL net (local + hierarchical labels on the CM5
# sheets) -> expose it hierarchically here (a global label collides: same_local_global_label).
# +3V3_RF/+3V3_AUX are new nets introduced by this port -> global is fine.
GLOBAL_NETS = {"+3V3_RF", "+3V3_AUX"}
GLOBAL_NETS = {"+3V3_RF", "+3V3_AUX", "PCIE_PWR_EN"}
HIER_NETS = {"+5v"}
# from KiCad libs (renamed to full lib_id)
add_from("power:PWR_FLAG", open(f"{KSS}/power.kicad_sym").read(), "PWR_FLAG")
@@ -207,6 +207,32 @@ place("Device:C", "C_OUT5b", "47u/16V", "Capacitor_SMD:C_1210_3225Metric", 180,
# +5v is now sourced by this buck -> PWR_FLAG co-located on L5 pin2 (+5v)
p5x, p5y = pin_abs(l5, "Device:L", "2"); emit_flag(p5x, p5y, "P5V")
# ---- STAGE 3: U_BUCK33R 15V -> +3V3_RF 4A (LM61460-Q1, sync) --------------------
# FB divider: VREF=1.0V -> Rfbt/Rfbb=2.32 -> 23.2k/10.0k = 3.32V.
# Same support set as stage 2 (RT 31.6k ~420kHz, L 4.7uH/7A: ripple ~1.3A = 33% of 4A).
# BIAS -> +3V3_RF (datasheet: BIAS>=3.1V uses output LDO path; falls back to VIN below).
# EN <- PCIE_PWR_EN (CM5 Module1 pin 106, global net) + 100k pull-down (= reference R14)
# so the Wi-Fi rail stays OFF until the CM5 asserts it.
place("CM5IO:LM61460-Q1", "U_BUCK33R", "LM61460-Q1", "Package_SO:Texas_HTSSOP-14-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3.155x3.255mm_ThermalVias",
230, 150, {'8': 'VIN_PROT', '12': 'VIN_PROT', '7': 'PCIE_PWR_EN', '1': '+3V3_RF', '2': 'VCC33',
'6': 'RT33', '5': 'PG33', '4': 'FB33', '10': 'SW33', '14': 'BOOT33', '13': 'RBOOT33',
'9': GND, '11': GND, '3': GND, '15': GND})
l33 = place("Device:L", "L33", "4.7uH/7A", "Inductor_SMD:L_Bourns_SRP1245A", 270, 138, {'1': 'SW33', '2': '+3V3_RF'})
place("Device:C", "C_BOOT33", "100n", "Capacitor_SMD:C_0402_1005Metric", 260, 132, {'1': 'SW33', '2': 'BOOT33'})
place("Device:R", "R_BOOT33", "4.7", "Resistor_SMD:R_0402_1005Metric", 265, 128, {'1': 'RBOOT33', '2': 'BOOT33'})
place("Device:R", "R_RT33", "31.6k", "Resistor_SMD:R_0402_1005Metric", 210, 158, {'1': 'RT33', '2': GND})
place("Device:R", "R_PG33", "100k", "Resistor_SMD:R_0402_1005Metric", 255, 143, {'1': 'PG33', '2': '+3V3_RF'})
place("Device:R", "R_FBT33", "23.2k", "Resistor_SMD:R_0402_1005Metric", 285, 150, {'1': '+3V3_RF', '2': 'FB33'})
place("Device:R", "R_FBB33", "10.0k", "Resistor_SMD:R_0402_1005Metric", 285, 158, {'1': 'FB33', '2': GND})
place("Device:R", "R_EN33", "100k", "Resistor_SMD:R_0402_1005Metric", 200, 165, {'1': 'PCIE_PWR_EN', '2': GND})
place("Device:C", "C_VCC33", "1u", "Capacitor_SMD:C_0402_1005Metric", 220, 158, {'1': 'VCC33', '2': GND})
place("Device:C", "C_IN33a", "10u/50V", "Capacitor_SMD:C_1210_3225Metric", 215, 145, {'1': 'VIN_PROT', '2': GND})
place("Device:C", "C_IN33b", "10u/50V", "Capacitor_SMD:C_1210_3225Metric", 220, 145, {'1': 'VIN_PROT', '2': GND})
place("Device:C", "C_OUT33a", "47u/16V", "Capacitor_SMD:C_1210_3225Metric", 240, 165, {'1': '+3V3_RF', '2': GND})
place("Device:C", "C_OUT33b", "47u/16V", "Capacitor_SMD:C_1210_3225Metric", 245, 165, {'1': '+3V3_RF', '2': GND})
# +3V3_RF is now sourced by this buck -> PWR_FLAG on L33 pin2 (replaces the E-key temp flag)
p33x, p33y = pin_abs(l33, "Device:L", "2"); emit_flag(p33x, p33y, "P33R")
# ---- file scaffold ----------------------------------------------------------------
libsyms = "\n".join(blk for blk, _ in LIBS.values())
sheet = ('(kicad_sch\n\t(version 20231120)\n\t(generator "eeschema")\n\t(generator_version "8.0")\n'