Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN

- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
  inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
  CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
  stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
  the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
  SPICE 17 pass / 2 benign warn / 0 fail

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

tools/build_ekey.py

@@ -211,19 +211,13 @@ place_rc("Device:R", "R_E1", "10k", "Resistor_SMD:R_0402_1005Metric", g(215.0),
 place_rc("Device:R", "R_E2", "10k", "Resistor_SMD:R_0402_1005Metric", g(225.0), g(80.0), loc_label, "WIFI_DISABLE2#", "+3V3_RF")
 
 # decoupling caps: pin1 -> +3V3_RF ; pin2 -> GND
-c_e1_pin1 = None
 for i, (ref, val) in enumerate([("C_E1", "10u"), ("C_E2", "100n"), ("C_E3", "100n")]):
     cx = g(215.0 + i * 7.62); cy = g(110.0)
     body.append(passive("Device:C", ref, val, "Capacitor_SMD:C_0402_1005Metric", cx, cy, ref))
-    p1 = (cx, round(cy - 3.81, 2))
-    body.append(glob_label("+3V3_RF", p1[0], p1[1], 90))                    # pin1
+    body.append(glob_label("+3V3_RF", cx, round(cy - 3.81, 2), 90))         # pin1
     body.append(gnd_sym(cx, round(cy + 3.81, 2), ref + "g"))               # pin2 -> GND symbol
-    if ref == "C_E1": c_e1_pin1 = p1
 
-# one PWR_FLAG to drive +3V3_RF until the power-sheet buck exists.
-# Co-locate its pin directly on an existing +3V3_RF node (C_E1 pin1) so it binds.
-# REMOVE this flag once the power sheet's buck drives +3V3_RF (else dual-driver ERC).
-body.append(pwr_flag(c_e1_pin1[0], c_e1_pin1[1], "33RF"))
+# +3V3_RF is driven by the Power sheet's U_BUCK33R (PWR_FLAG lives there).
 
 # ---- file scaffold -----------------------------------------------------------------
 libsyms = "\n".join([DEV_R, DEV_C, PWR_GND, pflag, sock])