Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN

- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
  inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
  CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
  stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
  the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
  SPICE 17 pass / 2 benign warn / 0 fail

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

carrier/CM5_HighSpeed.kicad_sch

@@ -12684,9 +12684,11 @@
 		(at 38.1 144.78)
 		(uuid "3e94757c-62b4-5b7d-9eb9-0bce1d18da64")
 	)
-	(no_connect
-		(at 38.1 30.48)
-		(uuid "22043a85-7370-5a2b-9195-7034c3f95e65")
+	(global_label "PCIE_PWR_EN"
+		(shape input)
+		(at 38.1 30.48 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "ec1f5dd4-69da-5539-9a4f-28c69e37960f")
 	)
 	(global_label "PCIE_nCLKREQ"
 		(shape input)