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Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN

Browse Source 
- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
  inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
  CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
  stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
  the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
  SPICE 17 pass / 2 benign warn / 0 fail

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
noise
2026-07-01 22:11:24 -04:00
parent d72f3a4bd8
commit 261bf48bb4
6 changed files with 594 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
carrier/CM5_HighSpeed.kicad_sch
View File

@@ -12684,9 +12684,11 @@
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13
carrier/M2_Ekey.kicad_sch
View File

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545
carrier/Power.kicad_sch
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