Power stage 3: LM61460-Q1 15V->+3V3_RF 4A buck; EN from CM5 PCIE_PWR_EN

- Second LM61460-Q1 (U_BUCK33R), FB 23.2k/10.0k -> 3.32V (SPICE: vfb 0.994V,
  inrush settles 3.32V); shared BOM with stage 2 (L 4.7uH/7A, RT 31.6k ~420kHz)
- BIAS -> +3V3_RF (datasheet-valid >=3.1V, falls back to VIN below)
- EN <- PCIE_PWR_EN: Module1 pin 106 NC swapped for a global label on
  CM5_HighSpeed + 100k pull-down (mirrors reference R14) so the Wi-Fi rail
  stays off until CM5 asserts it; netlist-verified 3-node net
- Removed the E-key temp PWR_FLAG (#FLG33RF); buck PWR_FLAG on L33.2 is now
  the sole +3V3_RF driver
- Verify: ERC 133->133 zero new; analyzer +49/-0 zero regressions;
  SPICE 17 pass / 2 benign warn / 0 fail

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

PORT_STATUS.md

@@ -6,25 +6,23 @@
 
 ## ▶ RESUME HERE (session handoff, 2026-07-01)
 
-**State:** branch `port/strip-phase`, HEAD `fd627f5`, working tree clean (only unrelated
-`refs/.history` submodule blip). Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`, `CM5_HighSpeed`
-(reference, stripped), `M2_Ekey` (E-key, done), `Power` (stages 1–2 done). Baseline anchor:
-`analysis/baseline/carrier_stripped.json`.
+**State:** branch `port/strip-phase`. Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`,
+`CM5_HighSpeed` (reference, stripped), `M2_Ekey` (E-key, done), `Power` (stages 1–3 done).
+Baseline anchor: `analysis/baseline/carrier_stripped.json`.
 
 **Done:** strip phase (microSD/HDMI/MIPI/PCIe-M2); M.2 E-key sheet (PCIe ×1 to CM5); Power
 stage 1 (LM74700 ideal-diode input protection → `VIN_PROT`); Power stage 2 (LM61460-Q1
-15→`+5v` 5 A sync buck, SPICE-verified 5.02 V). Current whole-design **ERC = 133** (all
-pre-existing types; a good edit adds **zero new**).
+15→`+5v` 5 A sync buck, SPICE-verified 5.02 V); Power stage 3 (LM61460-Q1 15→`+3V3_RF` 4 A,
+SPICE-verified 3.32 V; EN ← CM5 `PCIE_PWR_EN`/106 + 100k pull-down like reference R14; E-key
+temp PWR_FLAG removed — buck is the sole `+3V3_RF` driver). Current whole-design **ERC = 133**
+(all pre-existing types; a good edit adds **zero new**).
 
-**NEXT ACTION → Power Stage 3: `U_BUCK33R` 15→`+3V3_RF` 4 A.** Edit `tools/build_power.py`,
-append a Stage-3 block (copy the Stage-2 pattern): reuse the `CM5IO:LM61460-Q1` symbol; FB
-divider for 3.3 V → ratio 2.3 → `R_FBT 23.2k / R_FBB 10.0k` (SPICE-verify vfb=1.0 V @ 3.32 V);
-same L/Cin/Cout/boot/RT support. Then **(a)** delete the E-key temp `PWR_FLAG` on `+3V3_RF`
-(`#FLG33RF` in `carrier/M2_Ekey.kicad_sch` via build_ekey — the buck is the real driver now),
-and **(b)** wire the buck `EN` ← CM5 `PCIE_PWR_EN` (Module1 pin 106, currently NC on
-`CM5_HighSpeed`) for SW radio-power control. `+3V3_RF` is a NEW net → keep it a **global** label
-(no `same_local_global_label` risk, unlike `+5v`). Then Stage 4 (`+3V3_AUX`, TPS54202 28 V),
-then the GPS + PPS sheet.
+**NEXT ACTION → Power Stage 4: `U_BUCK33A` 15→`+3V3_AUX` ~1 A.** Candidate part TPS54202
+(28 V sync) — datasheet-verify first (KiCad has `Regulator_Switching:TPS54202DDC`). One check
+that MUST pass: the SMBJ18A clamp (~29 V at rated Ipp) vs the part's VIN abs-max — if the
+datasheet says <30 V abs-max, pick a 36 V-class sync part instead (LMR51430/TPS54360-class)
+or justify why the surge case is acceptable. FB divider per that part's VREF; SPICE-verify.
+`+3V3_AUX` is a NEW net → **global** label. Then the GPS + PPS sheet, then power-budget review.
 
 **How to build/verify (every change):**
 - Sheets are generated wholesale — edit `tools/build_ekey.py` / `tools/build_power.py`, then
@@ -134,7 +132,8 @@ Notes that bit us (don't re-learn the hard way):
 4. **Power sheet** (`carrier/Power.kicad_sch`, generated by `tools/build_power.py`) — staged, **sync + datasheet-built parts** (user choice). **Spec rating fix:** the spec's buck candidates miss its own ≥20V-Vin rule (TPS54424=17V, TPS54560=async) — selecting synchronous ≥30V parts instead (LM61460-class 6A for +5V & +3V3_RF/4A; TPS54202 28V for +3V3_AUX), each verified vs datasheet before commit.
    - **Stage 1 — input protection ✅ DONE.** J_PWR(15V) → D_REV `LM74700-Q1` ideal-diode + Q_REV N-FET (reverse-polarity/-current) → `VIN_PROT`; `SMBJ18A` TVS + 100µF/25V ∥ 10µF/50V bulk; C_VCAP charge-pump cap. Netlist-verified topology; ERC 133→133 (zero new); analyzer 0 regressions. **Confirm vs LM74700-Q1 datasheet:** C_VCAP value, EN-to-+15V_IN, FET pick (Vds≥30V, SOA/inrush) + optional gate R.
    - **Stage 2 — U_BUCK5 15→`+5v` 5A ✅ DONE.** `LM61460-Q1` (6A, 42V absmax sync; **custom symbol built from the datasheet** → `carrier/CM5IO.kicad_sym` as `CM5IO:LM61460-Q1`, fp `Package_SO:Texas_HTSSOP-14-1EP…ThermalVias`). VREF=1.0V → FB divider R_FBT5 40.2k / R_FBB5 10.0k = **5.02V (SPICE-confirmed vfb=1.0V)**. L5 4.7µH, Cout 2×47µF/16V, Cin 2×10µF/50V, Cboot 100n+Rboot 4.7Ω, RT 31.6k(~400kHz), BIAS→+5v, EN→VIN_PROT, PGOOD 100k→+5v. **`+5v` kept HIERARCHICAL** (pre-existing carrier net; global would collide `same_local_global_label`) — Power sheet exposes a `+5v` sheet pin, tied into the root `+5v` net; netlist-verified it drives Module1 + GPIO + USB. ERC 133→133 (zero new); analyzer +32 added **0 regressions**; SPICE 12/13 pass, 1 benign warn (L5/Cboot mis-detected as LC filter). **Confirm vs datasheet:** RT freq, L sat ≥7A, EP=pad15, optional EN UVLO divider.
-   - **Stage 3** U_BUCK33R 15→3.3V 4A → `+3V3_RF` (then REMOVE the E-key temp PWR_FLAG; wire buck EN ← CM5 `PCIE_PWR_EN`/106). **Stage 4** U_BUCK33A 15→3.3V 1A → `+3V3_AUX`. SPICE-validate each feedback divider.
+   - **Stage 3 — U_BUCK33R 15→`+3V3_RF` 4A ✅ DONE.** Second `LM61460-Q1` (shared BOM with stage 2: L 4.7µH/7A ripple ~1.3A=33%, Cin 2×10µ/50V, Cout 2×47µ/16V, RT 31.6k ~420kHz, Cboot 100n+Rboot 4.7). FB divider R_FBT33 23.2k / R_FBB33 10.0k = **3.32V (SPICE: vfb 0.994V, inrush settles 3.32V)**. BIAS→`+3V3_RF` (datasheet: valid ≥3.1V, auto-falls back to VIN below). **EN ← CM5 `PCIE_PWR_EN`** (Module1 pin 106: NC swapped for a global label on `CM5_HighSpeed`) + **R_EN33 100k pull-down** (mirrors reference R14 — netlist-verified `Module1.106 + U_BUCK33R.7 + R_EN33.1`) so the Wi-Fi rail is OFF until the CM5 asserts it. **E-key temp `#FLG33RF` PWR_FLAG removed** (build_ekey); the buck's PWR_FLAG on L33.2 is now the sole `+3V3_RF` driver — netlist shows buck + all 4 J_E power pins + pull-ups + decoupling on one net. Verify: ERC 133→133 zero new; analyzer +49 added **0 regressions**; SPICE 17 pass / 2 benign warn (the L/C_BOOT "LC filter" mis-detect, once per buck) / 0 fail. (Note: `kicad-cli` netlist export prints a pre-existing "annotation errors" warning — un-numbered generated refdeses like `J_E`/`J_PWR`; present at fd627f5 too, cosmetic.)
+   - **Stage 4** U_BUCK33A 15→3.3V ~1A → `+3V3_AUX`. SPICE-validate the feedback divider (see NEXT ACTION above for the part-selection gate).
 5. **GPS + PPS distribution**: GPS connector (PPS+UART+3V3+GND); PPS → TVS → Schmitt (LVC1G17) →
    fan-out: CM5 `Ethernet_SYNC_OUT` (J2 pin-6 net, 3.3V, no translator) + 2 header taps. SPICE/timing check.