docs: power-budget review section + refreshed RESUME header (close-out complete)

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

PORT_STATUS.md

@@ -4,32 +4,33 @@
 > `.claude/skills/kicad-port/SKILL.md` (the mandatory workflow/verify-loop), then
 > `CM5_Carrier_Design.md` (frozen rev-A spec).
 
-## ▶ RESUME HERE (session handoff, 2026-07-02 — work paused here, schematic capture COMPLETE)
+## ▶ RESUME HERE (session handoff, 2026-07-04 — close-out passes COMPLETE, ready for layout prep)
 
-**State:** branch `port/strip-phase`, HEAD `fb19caa`, working tree clean (only the unrelated
+**State:** branch `port/strip-phase` (merged → `main`), working tree clean. Sheets in
-`refs/.history` submodule blip). Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`,
+`carrier/`: root `CM5IO`, `CM5_GPIO`, `CM5_HighSpeed` (reference, stripped), `M2_Ekey`,
-`CM5_HighSpeed` (reference, stripped), `M2_Ekey`, `Power` (stages 1–4), `GPS_PPS`. **ALL
+`Power` (stages 1–4), `GPS_PPS`. All rev-A blocks captured; **power-budget review +
-rev-A circuit blocks are now captured.** Baseline anchor: `analysis/baseline/carrier_stripped.json`.
+datasheet confirms + hygiene pass done** (see "Power-budget review" section below).
+Baseline anchor: `analysis/baseline/carrier_stripped.json`. Whole-design **ERC = 133**
+(all pre-existing types; a good edit adds **zero new**); kicad-cli annotation warning GONE;
+BOM sane (105 components, all with value+footprint); SPICE 24 pass / 2 benign warn / 0 fail.
 
-**Done:** strip phase (microSD/HDMI/MIPI/PCIe-M2); M.2 E-key sheet (PCIe ×1); Power stage 1
+**Close-out fixes landed (2026-07-04):**
-(LM74700 → `VIN_PROT`), stage 2 (LM61460-Q1 → `+5v` 5 A, SPICE 5.02 V), stage 3 (LM61460-Q1 →
+- Removed orphaned `U12` (RT9742) + `C13` — fed the stripped `HDMI_5v` rail (ref-netlist-proven).
-`+3V3_RF` 4 A, SPICE 3.32 V, EN ← `PCIE_PWR_EN`), stage 4 (TPS54202 → `+3V3_AUX` ~1 A, SPICE
+- **Cut J11 (USB-C prog) VBUS from `+5v`** + dropped `R9` bleed — host VBUS would have
-3.315 V); **GPS + PPS sheet** (`carrier/GPS_PPS.kicad_sch` via `tools/build_gps.py`: J_GPS
+  paralleled U_BUCK5's output (reference is USB-C-powered; carrier is not). VBUS pins NC;
-5-pin per Pinout_BOM §6, PPS → PESD3V3 TVS → 74LVC1G17 @ +3V3_AUX → `PPS_CLEAN` → Rs 33Ω →
+  CC1/CC2 stay wired to CM5 (module implements the PD sink per SC1466 — supersedes the
-`SYNC_OUT` (CM5 pin 18 + J2.6) + J_PPS1/J_PPS2 taps; NMEA on **UART2 GPIO4/GPIO5** per
+  spec's discrete 5.1 k Rd); D± unchanged → rpiboot unaffected (CM5 has no VBUS-sense pin).
-correction C2 — netlist: GPIO4 = Module1.54+J8.7+J_GPS.3, GPIO5 = Module1.34+J8.29+J_GPS.2).
+- `C_BULK1` 100 µF **25 V→35 V** (sits on VIN_PROT where SMBJ18A clamps ≤29.2 V).
-The `SYNC_OUT`/`GPIO4`/`GPIO5` local labels on CM5_GPIO were converted to **global** labels
+- Refdes hygiene: all generated refs digit-terminated (`J_E`→`J_E1`, `C_VCAP`→`C_VCAP1`, …,
-(names unchanged, nothing else used them) to reach the new sheet without root plumbing.
+  `#FLG15IN`→`#FLG15IN1`); generator emit-helpers now normalize tags. Title blocks: carrier
-Current whole-design **ERC = 133** (all pre-existing types; a good edit adds **zero new**).
+  identity, rev A, CM5IO derivation credited.
 
-**NEXT ACTION → design-review + close-out passes** (no new blocks):
+**NEXT ACTION → layout prep:** copy DF40 (CM5 connector) placement from the reference PCB,
-1. **Power-budget review** of the whole tree (loads vs ratings; the kicad skill's power-tree
+then floorplan: Power stage entry edge, RF keepout around M.2, PPS trace hygiene.
-   check) + re-read PORT_STATUS "Confirm vs datasheet" leftovers (stage-1 C_VCAP/FET pick,
+Open items (decide at layout/BOM time, none block layout start — details in the review section):
-   stage-2/3 L saturation ≥ Ipk, RT freq).
+per-port USB-A ILIM vs shared 1.19 A (spec deviation), ESD array on J11 D± (spec BOM item 12,
-2. **Hygiene pass** (checklist in kicad-port skill): refdes numbering (un-numbered generated
+reference shipped without), M.2 socket contact rating ≥0.9 A/pin, J8 header draw guidance
-   refs `J_E`/`J_PWR`/`U_BUCK5`… trip kicad-cli "annotation errors" — decide whether to number
+(≤1 A on 5 V, ≤400 mA on 3.3 V), L33A1 Isat 2.5 A vs TPS54202 fault current (hiccup-protected).
-   them), title blocks, netlist-vs-BOM sanity, design notes.
-3. Then merge `port/strip-phase` → main and start layout prep (DF40 placement copy from ref).
 
 **How to build/verify (every change):**
 - Sheets are generated wholesale — edit `tools/build_ekey.py` / `tools/build_power.py`, then
@@ -43,6 +44,36 @@ Current whole-design **ERC = 133** (all pre-existing types; a good edit adds **z
   bind; PWR_FLAG/GND must sit on a real pin coord; pre-existing `+5v` is hierarchical (not global);
   type feedback pins `passive`; connector/module pin types may need remodeling for cross-part ERC.
 
+## Power-budget review (2026-07-04, all datasheet-backed)
+
+Tree: 15 V (J_PWR1, Phoenix MKDS-1.5 ≈13.5 A) → LM74700+CSD18540 ideal diode → `VIN_PROT`
+→ 3 bucks. Worst-case input ≈ 40 W / 15 V ≈ **2.9 A** — huge connector/FET margin.
+
+| Rail | Source | Rating | Worst-case load | Verdict |
+|------|--------|--------|-----------------|---------|
+| `VIN_PROT` | LM74700 + CSD18540 (60 V, ~2 mΩ) | — | 2.9 A (≈20 mW in FET) | ✅ |
+| `+5v` | U_BUCK51 LM61460 (6 A; HS ILIM 8.9–11.5 A) | 6 A | CM5 (0.4 idle/0.9 typ/~3 A heavy, incl. its 3V3+1V8 outputs) + USB-A ≤1.53 A (U6 ILIM) + fan ~0.3 A + J8 5 V user | ✅ if J8 draw documented ≤1 A |
+| `+3V3_RF` | U_BUCK33R1 LM61460 (6 A) | 4 A design | AW7915 3–3.5 A TX bursts | ✅ ~2.5 A headroom |
+| `+3V3_AUX` | U_BUCK33A1 TPS54202 (2 A) | ~1 A design | GPS ~0.1 A + 74LVC1G17 ~mA | ✅ |
+| `CM5_3.3V` (module out) | CM5 | **600 mA total** | LEDs+magjack+U5 ≈50 mA + J8 3.3 V user | ✅ if J8 draw documented ≤400 mA |
+| `CM5_1.8V` (module out) | CM5 | 600 mA | R4 = nf → unloaded | ✅ |
+
+**Datasheet confirms (closes all "confirm vs datasheet" leftovers):**
+- LM74700: C_VCAP min 0.1 µF, rec ≥10×Ciss(FET) → our 1 µF ✓; EN→ANODE = documented always-on ✓.
+- LM61460: RT 33.2 k→400 kHz table row; our 31.6 k ≈ 420 kHz, in 200 k–2.2 M range ✓.
+  Ipk @5 A ≈ 5.8 A < HS ILIM min 8.9 A ✓.
+- L5/L33 (Bourns SRP1245A-4R7M): **Isat 15 A** > ILIM max 11.5 A ✓✓; Irms ~11 A ✓.
+- AP22653 (U6, R12=15 k): ILIM 0.94–1.53 A (typ 1.19 A, best-fit eqn ILIMIT_typ=30321/R^1.055),
+  **shared across both USB-A ports** — spec §5 wanted 0.9–1.2 A *per port*. Deviation kept
+  (reference-proven; protects the 5 V budget). Rev-B option: one AP22653 per port.
+- TPS54202: VIN abs-max 30 V vs SMBJ18A clamp ≤29.2 V — 0.8 V margin, accepted + documented.
+  L33A1 (10 µH/2.5 A): Ipk @1 A ≈ 1.26 A ✓; fault current before hiccup can brush ~3 A >
+  Isat — acceptable (hiccup-protected), consider Isat ≥3 A part at BOM time.
+
+**Sequencing:** module drives its own 3.3/1.8 rails after `PMIC_EN`; `+3V3_RF` EN gated by
+CM5 `PCIE_PWR_EN` (up only after boot) ✓; `+3V3_AUX` EN = UVLO divider (start 10.1 V /
+stop 8.6 V) so GPS runs whenever 15 V is healthy ✓.
+
 ## What this repo is
 
 Two intertwined goals: