Strip PCIe-M2 (M-key/NVMe) sheet; re-baseline stripped carrier

Drops the unused M.2 M-key/NVMe block — design is 1x M.2 E-key (Wi-Fi)
only, since the CM5 exposes a single PCIe x1 lane (datasheet SC1466),
reserved for the E-key. The 10 freed PCIE_* lanes are NC on Module1
unit 2, to be rewired to a fresh E-key sheet in the add phase.

- CM5_HighSpeed: retire PCIE_* labels/wires, NC pins 102,104,106,109,
  110,112,116,118,122,124
- root CM5IO: drop whole PCIe-M2 (sheet) block; strip dangling PCIE_*
  pins off the kept CM5_HighSpeed sheet symbol
- delete carrier/PCIe-M2.kicad_sch; clean .kicad_pro sheets array + ERC
  exclusion
- retire_block.py: add --drop-sheet FILE (remove whole (sheet) block +
  sheet_instances path)
- analysis/baseline/carrier_stripped.json: new add-phase diff anchor

Verify: ERC 136->133 (zero new violation types); analyzer diff +0/~0
(cumulative -41 removed vs original ref); netlist confirms +5v/+3.3v/
GND/+1.8v intact (U8's M2_3v3 was a local rail, not board +3.3v).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

PORT_STATUS.md

@@ -62,13 +62,16 @@ Usage: `python3 tools/retire_block.py <sheet> --symbols J7,U18 --nets 'SD_*' --n
 **Known gap (next improvement):** does NOT auto-prune orphaned power-label/wire *stubs* left after a
 connector is removed (e.g. leftover `+3.3v`/`HDMI_5v` labels). Those were cleaned manually — see git history.
 
-## Strip phase — DONE (microSD + HDMI + MIPI), ERC 182 → 136, 0 new violations, 0 regressions
+## Strip phase — DONE (microSD + HDMI + MIPI + PCIe-M2), ERC 182 → 133, 0 new violations, 0 regressions
 
 | Block | Sheet(s) | Command(s) (run with `--apply`) |
 |---|---|---|
 | **microSD** | CM5_GPIO | `--symbols J7,U18,C5 --nets 'SD_*' --nc-pins 57,61,62,63,67,69,75` |
 | **HDMI** | CM5_HighSpeed | `--symbols J22,J10 --nets 'HDMI0_*,HDMI1_*,HDMI_5v' --nc-pins 143,145,146,147,148,149,151,152,153,154,158,160,164,166,170,172,176,178,182,184,188,190,199,200` |
 | **MIPI/camera** | CM5_HighSpeed, CM5_GPIO, CM5IO(root) | (1) HighSpeed `--symbols J5,J16 --nets 'DPHY0_*,DPHY1_*,SCL1,SDA1' --nc-pins 115,117,121,123,127,129,133,135,139,141,175,177,181,183,187,189,193,194,195,196` (2) GPIO `--nc-pins 80,82,97,100` (3) root `--sheet-ports SCL0,SDA0,CAM_GPIO0,CAM_GPIO1` (4) HighSpeed `--symbols R8 --nets 'SCL0,SDA0'` (5) manual: remove 3 orphaned +3.3v labels + 2 wire stubs |
+| **PCIe-M2 (M-key/NVMe)** | CM5_HighSpeed, CM5IO(root), `.kicad_pro` | (1) HighSpeed `--nets 'PCIE_*' --nc-pins 102,104,106,109,110,112,116,118,122,124` (2) root `--drop-sheet PCIe-M2.kicad_sch` (3) root `--sheet-ports PCIE_CLK_P,PCIE_CLK_N,PCIE_TX_P,PCIE_TX_N,PCIE_nRST,PCIE_RX_P,PCIE_RX_N,PCIE_nCLKREQ,PCIE_PWR_EN,PCIE_nWAKE` (strip dangling HighSpeed sheet-symbol pins) (4) `git rm carrier/PCIe-M2.kicad_sch` (5) manual: remove PCIe-M2 entry from `.kicad_pro` `sheets` array + its ERC exclusion. **Design confirmed: 1× M.2 E-key (Wi-Fi) only, 0× M-key SSD** — the single CM5 PCIe ×1 lane is reserved for the E-key; the freed `PCIE_*` lanes (now NC on Module1 unit 2) will be rewired to the fresh E-key sheet in the add phase. |
+
+**`retire_block.py` gained `--drop-sheet FILE`**: removes the whole `(sheet …)` block by Sheetfile + its `sheet_instances` path (run on the parent sheet). `.kicad_pro` `sheets`-array + ERC-exclusion cleanup is still manual (next tool gap).
 
 Notes that bit us (don't re-learn the hard way):
 - **MIPI lanes are labeled `DPHY0_*`/`DPHY1_*`, NOT `MIPI*`.** The connectors J5/J16 are camera FFCs
@@ -80,10 +83,9 @@ Notes that bit us (don't re-learn the hard way):
 
 ## Next steps
 
-1. **Drop the PCIe-M2 sheet entirely** (NVMe M-key — not used; the M.2 **E-key** Wi-Fi will be a
+1. ~~Drop the PCIe-M2 sheet entirely~~ **DONE** (see strip table). Confirmed E-key-only (no M-key SSD).
-   FRESH sheet in the add phase, per design decision). Use `--sheet-ports` for its root hierarchical pins.
 2. **Re-baseline**: capture a new analyzer baseline of `carrier/` so the add phase diffs against the
-   stripped design, not the original reference.
+   stripped design, not the original reference. (`analyze_schematic.py carrier/CM5IO.kicad_sch -o analysis/baseline/carrier_stripped.json`)
 3. **Add phase**: 15V→5V buck front-end (reverse-protection + TVS), M.2 E-key (PCIe Gen2 ×1 +
    CLKREQ/PERST/RF_KILL + 3.3V), GPS connector, PPS distribution (GPS PPS → TVS → Schmitt buffer →
    fan-out: CM5 `Ethernet_SYNC_OUT` + 2 header taps). SPICE-validate the buck divider + PPS network.

carrier/CM5IO.kicad_pro

@@ -261,7 +261,6 @@
   "erc": {
     "erc_exclusions": [
       "power_pin_not_driven|1003300|1181100|66cf9899-100d-45fb-9b9f-8f866de8a3fe|00000000-0000-0000-0000-000000000000|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|",
-      "power_pin_not_driven|1524000|317500|2cecda96-8fc5-40d2-a9f4-ae1444adbd06|00000000-0000-0000-0000-000000000000|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005ed4bb5b|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005ed4bb5b|",
       "power_pin_not_driven|393700|1181100|0fc4267c-2119-444e-b3b2-d8a7bd88ec8a|00000000-0000-0000-0000-000000000000|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55/00000000-0000-0000-0000-00005cff706a|"
     ],
     "meta": {
@@ -834,10 +833,6 @@
     [
       "00000000-0000-0000-0000-00005cff706a",
       "CM5_GPIO ( Ethernet, GPIO, SDCARD)"
-    ],
-    [
-      "00000000-0000-0000-0000-00005ed4bb5b",
-      "PCIe-M2"
     ]
   ],
   "text_variables": {}

carrier/CM5IO.kicad_sch

@@ -1209,16 +1209,6 @@
 		)
 		(uuid "0f3c9e3a-9c59-4881-b27a-d0e982b3ea8e")
 	)
-	(wire
-		(pts
-			(xy 186.69 53.34) (xy 214.63 53.34)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "14f9e820-8d3f-4833-ac31-9b9e9028d8dc")
-	)
 	(wire
 		(pts
 			(xy 62.23 52.07) (xy 74.93 52.07)
@@ -1229,16 +1219,6 @@
 		)
 		(uuid "19ecf363-8282-4d88-8cbf-f045ad2274f8")
 	)
-	(wire
-		(pts
-			(xy 186.69 68.58) (xy 214.63 68.58)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "213a2af1-412b-47f4-ab3b-c5f43b6be7a6")
-	)
 	(wire
 		(pts
 			(xy 115.57 57.15) (xy 115.57 50.8)
@@ -1259,16 +1239,6 @@
 		)
 		(uuid "26eed24a-a6fe-4994-877d-88ca1bd022b3")
 	)
-	(wire
-		(pts
-			(xy 186.69 43.18) (xy 214.63 43.18)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "2d6718e7-f18d-444d-9792-ddf1a113460c")
-	)
 	(wire
 		(pts
 			(xy 72.39 80.01) (xy 83.82 80.01)
@@ -1309,16 +1279,6 @@
 		)
 		(uuid "532c6793-fcef-48e2-94ae-3d6f4bca00a7")
 	)
-	(wire
-		(pts
-			(xy 186.69 57.15) (xy 214.63 57.15)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "573ee3b8-d265-4b77-9337-75b96bd8afff")
-	)
 	(wire
 		(pts
 			(xy 113.03 48.26) (xy 113.03 62.23)
@@ -1329,16 +1289,6 @@
 		)
 		(uuid "59d43607-0f19-4477-88e6-8d4e79b5589b")
 	)
-	(wire
-		(pts
-			(xy 186.69 50.8) (xy 214.63 50.8)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "71c77456-1405-42e3-95ed-69e629de0558")
-	)
 	(wire
 		(pts
 			(xy 72.39 80.01) (xy 72.39 82.55)
@@ -1359,16 +1309,6 @@
 		)
 		(uuid "7aaa8496-fa91-4cdd-a95c-0fb4934a563f")
 	)
-	(wire
-		(pts
-			(xy 186.69 64.77) (xy 214.63 64.77)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "7f3eb118-a20c-4239-b800-c9211c66847d")
-	)
 	(wire
 		(pts
 			(xy 62.23 44.45) (xy 87.63 44.45)
@@ -1409,16 +1349,6 @@
 		)
 		(uuid "909b030b-fa1a-4fe8-b1ee-422b4d9e23cf")
 	)
-	(wire
-		(pts
-			(xy 186.69 72.39) (xy 214.63 72.39)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "a8690438-b6c5-46ae-bc23-906e22bda6c7")
-	)
 	(wire
 		(pts
 			(xy 43.18 82.55) (xy 46.99 82.55)
@@ -1429,16 +1359,6 @@
 		)
 		(uuid "b38f69e2-7f84-451a-9316-b038cdf98445")
 	)
-	(wire
-		(pts
-			(xy 186.69 59.69) (xy 214.63 59.69)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "b4f385c6-872a-4056-a543-aa8bf444002f")
-	)
 	(wire
 		(pts
 			(xy 39.37 82.55) (xy 43.18 82.55)
@@ -1519,16 +1439,6 @@
 		)
 		(uuid "e83e0227-ac0f-4180-82bd-68d3a7b56476")
 	)
-	(wire
-		(pts
-			(xy 186.69 45.72) (xy 214.63 45.72)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "f144a97d-c3f0-423f-b0a9-3f7dbc42478b")
-	)
 	(wire
 		(pts
 			(xy 62.23 57.15) (xy 115.57 57.15)
@@ -1539,16 +1449,6 @@
 		)
 		(uuid "f1f3a160-e530-44d2-9a4b-2d9f99bce435")
 	)
-	(wire
-		(pts
-			(xy 186.69 76.2) (xy 214.63 76.2)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "fa92842d-37e8-4687-b4f4-0cfd415b8d84")
-	)
 	(text "Connectors\n-------\nEthernet\nSDCARD\n40way RPI\nJumpers\nFan\nBattery"
 		(exclude_from_sim no)
 		(at 150.876 147.066 0)
@@ -3521,86 +3421,6 @@
 			)
 			(uuid "0f22151c-f260-4674-b486-4710a2c42a55")
 		)
-		(pin "PCIE_CLK_P" output
-			(at 186.69 57.15 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "fe8d9267-7834-48d6-a191-c8724b2ee78d")
-		)
-		(pin "PCIE_CLK_N" output
-			(at 186.69 59.69 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "0b21a65d-d20b-411e-920a-75c343ac5136")
-		)
-		(pin "PCIE_TX_P" output
-			(at 186.69 43.18 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "3cd1bda0-18db-417d-b581-a0c50623df68")
-		)
-		(pin "PCIE_TX_N" output
-			(at 186.69 45.72 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "d57dcfee-5058-4fc2-a68b-05f9a48f685b")
-		)
-		(pin "PCIE_nRST" output
-			(at 186.69 64.77 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "03c52831-5dc5-43c5-a442-8d23643b46fb")
-		)
-		(pin "PCIE_RX_P" input
-			(at 186.69 50.8 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "a1823eb2-fb0d-4ed8-8b96-04184ac3a9d5")
-		)
-		(pin "PCIE_RX_N" input
-			(at 186.69 53.34 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "29e78086-2175-405e-9ba3-c48766d2f50c")
-		)
-		(pin "PCIE_nCLKREQ" input
-			(at 186.69 68.58 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "94a873dc-af67-4ef9-8159-1f7c93eeb3d7")
-		)
 		(pin "+3.3v" input
 			(at 129.54 76.2 180)
 			(effects
@@ -3631,26 +3451,6 @@
 			)
 			(uuid "9bb20359-0f8b-45bc-9d38-6626ed3a939d")
 		)
-		(pin "PCIE_PWR_EN" output
-			(at 186.69 72.39 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "e445000d-94a3-4ed1-b023-6aae972d0a39")
-		)
-		(pin "PCIE_nWAKE" input
-			(at 186.69 76.2 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "31cb0f66-393a-491f-95aa-c50644299a5d")
-		)
 		(instances
 			(project "CM5IO"
 				(path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55"
@@ -3659,155 +3459,6 @@
 			)
 		)
 	)
-	(sheet
-		(at 214.63 34.29)
-		(size 27.94 52.07)
-		(fields_autoplaced yes)
-		(stroke
-			(width 0.152)
-			(type solid)
-			(color 132 0 132 1)
-		)
-		(fill
-			(color 255 255 255 0.0000)
-		)
-		(uuid "00000000-0000-0000-0000-00005ed4bb5b")
-		(property "Sheetname" "PCIe-M2"
-			(at 214.63 33.5786 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left bottom)
-			)
-		)
-		(property "Sheetfile" "PCIe-M2.kicad_sch"
-			(at 214.63 86.9444 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left top)
-			)
-		)
-		(pin "PCIE_CLK_P" input
-			(at 214.63 57.15 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "ee27d19c-8dca-4ac8-a760-6dfd54d28071")
-		)
-		(pin "PCIE_CLK_N" input
-			(at 214.63 59.69 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "9b0a1687-7e1b-4a04-a30b-c27a072a2949")
-		)
-		(pin "PCIE_TX_P" input
-			(at 214.63 43.18 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "c01d25cd-f4bb-4ef3-b5ea-533a2a4ddb2b")
-		)
-		(pin "PCIE_TX_N" input
-			(at 214.63 45.72 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "9e1b837f-0d34-4a18-9644-9ee68f141f46")
-		)
-		(pin "PCIE_nCLKREQ" output
-			(at 214.63 68.58 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "63ff1c93-3f96-4c33-b498-5dd8c33bccc0")
-		)
-		(pin "PCIE_nRST" input
-			(at 214.63 64.77 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "b88717bd-086f-46cd-9d3f-0396009d0996")
-		)
-		(pin "PCIE_RX_P" output
-			(at 214.63 50.8 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "61fe293f-6808-4b7f-9340-9aaac7054a97")
-		)
-		(pin "PCIE_RX_N" output
-			(at 214.63 53.34 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "2f215f15-3d52-4c91-93e6-3ea03a95622f")
-		)
-		(pin "+5v" input
-			(at 242.57 64.77 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify right)
-			)
-			(uuid "0217dfc4-fc13-4699-99ad-d9948522648e")
-		)
-		(pin "PCIE_PWR_EN" input
-			(at 214.63 72.39 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "97775b76-6935-4c0f-9fc9-91db55c7f4d2")
-		)
-		(pin "PCIE_nWAKE" output
-			(at 214.63 76.2 180)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-			(uuid "29caf48f-b190-47ea-a0b4-a078d43caa04")
-		)
-		(instances
-			(project "CM5IO"
-				(path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55"
-					(page "4")
-				)
-			)
-		)
-	)
 	(sheet_instances
 		(path "/"
 			(page "1")

carrier/CM5_HighSpeed.kicad_sch

@@ -7644,16 +7644,6 @@
 		)
 		(uuid "27e3c71f-5a63-4710-8adf-b600b805ce02")
 	)
-	(wire
-		(pts
-			(xy 31.75 38.1) (xy 38.1 38.1)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "2938bf2d-2d32-4cb0-9d4d-563ea28ffffa")
-	)
 	(wire
 		(pts
 			(xy 35.56 109.22) (xy 38.1 109.22)
@@ -7734,16 +7724,6 @@
 		)
 		(uuid "2f5467a7-bd49-433c-92f2-60a842e66f7b")
 	)
-	(wire
-		(pts
-			(xy 31.75 27.94) (xy 38.1 27.94)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "2f75af73-81af-4c13-9b1c-587f6551682a")
-	)
 	(wire
 		(pts
 			(xy 180.34 48.26) (xy 196.85 48.26)
@@ -7904,16 +7884,6 @@
 		)
 		(uuid "4faeed13-cd8a-4bdc-8d48-1ca1fe386979")
 	)
-	(wire
-		(pts
-			(xy 38.1 43.18) (xy 31.75 43.18)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "5099f397-6fe7-454f-899c-34e2b5f22ca7")
-	)
 	(wire
 		(pts
 			(xy 229.87 147.32) (xy 240.03 147.32)
@@ -7924,16 +7894,6 @@
 		)
 		(uuid "51f5536d-48d2-4807-be44-93f427952b0e")
 	)
-	(wire
-		(pts
-			(xy 31.75 30.48) (xy 38.1 30.48)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "5243fe6a-ae55-40b5-8db1-ec9d4b04147b")
-	)
 	(wire
 		(pts
 			(xy 99.06 132.08) (xy 101.6 132.08)
@@ -7944,16 +7904,6 @@
 		)
 		(uuid "524d7aa8-362f-459a-b2ae-4ca2a0b1612b")
 	)
-	(wire
-		(pts
-			(xy 31.75 53.34) (xy 38.1 53.34)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "53fda1fb-12bd-4536-80e1-aab5c0e3fc58")
-	)
 	(wire
 		(pts
 			(xy 82.55 177.8) (xy 82.55 185.42)
@@ -8044,16 +7994,6 @@
 		)
 		(uuid "5cdb7416-8115-42e3-a14b-940e7e48428d")
 	)
-	(wire
-		(pts
-			(xy 38.1 45.72) (xy 31.75 45.72)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "6474aa6c-825c-4f0f-9938-759b68df02a5")
-	)
 	(wire
 		(pts
 			(xy 101.6 93.98) (xy 101.6 101.6)
@@ -8234,16 +8174,6 @@
 		)
 		(uuid "87a0ffb1-5477-4b20-a3ac-fef5af129a33")
 	)
-	(wire
-		(pts
-			(xy 31.75 35.56) (xy 38.1 35.56)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "89bd1fdd-6a91-474e-8495-7a2ba7eb6260")
-	)
 	(wire
 		(pts
 			(xy 101.6 139.7) (xy 101.6 147.32)
@@ -8264,16 +8194,6 @@
 		)
 		(uuid "8afe1dbf-1187-4362-8af8-a90ca839a6b3")
 	)
-	(wire
-		(pts
-			(xy 31.75 25.4) (xy 38.1 25.4)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "8b022692-69b7-4bd6-bf38-57edecf356fa")
-	)
 	(wire
 		(pts
 			(xy 180.34 80.01) (xy 196.85 80.01)
@@ -8284,16 +8204,6 @@
 		)
 		(uuid "8c4772bb-de72-4bbc-8951-f76ac882c05f")
 	)
-	(wire
-		(pts
-			(xy 31.75 50.8) (xy 38.1 50.8)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "929c74c0-78bf-4efe-a778-fa328e951865")
-	)
 	(wire
 		(pts
 			(xy 151.13 78.74) (xy 134.62 78.74)
@@ -8674,16 +8584,6 @@
 		)
 		(uuid "d5a7688c-7438-4b6d-999f-4f2a3cb18fd6")
 	)
-	(wire
-		(pts
-			(xy 99.06 35.56) (xy 105.41 35.56)
-		)
-		(stroke
-			(width 0)
-			(type solid)
-		)
-		(uuid "d5c86a84-6c8b-48b5-b583-2fe7052421ab")
-	)
 	(wire
 		(pts
 			(xy 101.6 71.12) (xy 101.6 93.98)
@@ -9355,42 +9255,6 @@
 		)
 		(uuid "02b1295e-cf95-47ff-9c57-f8ada28f2e94")
 	)
-	(hierarchical_label "PCIE_PWR_EN"
-		(shape output)
-		(at 31.75 30.48 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "1dacd626-a559-4363-9eb3-77dde5d16024")
-	)
-	(hierarchical_label "PCIE_CLK_P"
-		(shape output)
-		(at 31.75 35.56 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "25247d0c-5910-484b-9651-5750d422a450")
-	)
-	(hierarchical_label "PCIE_RX_N"
-		(shape input)
-		(at 31.75 45.72 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "4aee84d1-0859-48ac-a053-5a981ee1b24a")
-	)
 	(hierarchical_label "+5v"
 		(shape input)
 		(at 191.77 147.32 180)
@@ -9403,18 +9267,6 @@
 		)
 		(uuid "4d55ddc7-73be-49f7-98ea-a0ba474cbdb0")
 	)
-	(hierarchical_label "PCIE_nCLKREQ"
-		(shape input)
-		(at 31.75 25.4 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "59142adb-6887-41fc-851e-9a7f51511d60")
-	)
 	(hierarchical_label "ID_SC"
 		(shape input)
 		(at 185.42 119.38 180)
@@ -9427,18 +9279,6 @@
 		)
 		(uuid "5b04e20f-8575-4362-b040-2e2133d670c8")
 	)
-	(hierarchical_label "PCIE_RX_P"
-		(shape input)
-		(at 31.75 43.18 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "5fc4054a-b929-433e-a947-747fb7ed003d")
-	)
 	(hierarchical_label "GPIO_VREF"
 		(shape input)
 		(at 196.85 104.14 180)
@@ -9487,18 +9327,6 @@
 		)
 		(uuid "69f75991-c8c0-49a9-aed8-daa6ca9a5d73")
 	)
-	(hierarchical_label "PCIE_TX_P"
-		(shape output)
-		(at 31.75 50.8 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "811f5389-c208-4640-ab1a-b454491bb330")
-	)
 	(hierarchical_label "ID_SD"
 		(shape input)
 		(at 185.42 121.92 180)
@@ -9511,54 +9339,6 @@
 		)
 		(uuid "8e715b73-353f-4cfc-aa33-1eac54b89b6c")
 	)
-	(hierarchical_label "PCIE_nWAKE"
-		(shape input)
-		(at 31.75 27.94 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "a8b35311-4f8b-4438-aa47-dca2f66d55c9")
-	)
-	(hierarchical_label "PCIE_CLK_N"
-		(shape output)
-		(at 31.75 38.1 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "b6f041a4-3ea0-418b-94a2-50c938beafa2")
-	)
-	(hierarchical_label "PCIE_nRST"
-		(shape output)
-		(at 105.41 35.56 0)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify left)
-		)
-		(uuid "bb673c7a-d2b0-45b0-bfe2-0b113c092a77")
-	)
-	(hierarchical_label "PCIE_TX_N"
-		(shape output)
-		(at 31.75 53.34 180)
-		(fields_autoplaced yes)
-		(effects
-			(font
-				(size 1.27 1.27)
-			)
-			(justify right)
-		)
-		(uuid "d4876469-b949-49ce-b8fe-43cb458692a4")
-	)
 	(symbol
 		(lib_id "power:GND")
 		(at 101.6 152.4 0)
@@ -12904,4 +12684,44 @@
 		(at 38.1 144.78)
 		(uuid "3e94757c-62b4-5b7d-9eb9-0bce1d18da64")
 	)
+	(no_connect
+		(at 38.1 25.4)
+		(uuid "aab94d9f-4d88-55fd-8963-e421713879b9")
+	)
+	(no_connect
+		(at 38.1 27.94)
+		(uuid "bf767c9b-22d7-5638-8a4e-bb8fee0ab324")
+	)
+	(no_connect
+		(at 38.1 30.48)
+		(uuid "22043a85-7370-5a2b-9195-7034c3f95e65")
+	)
+	(no_connect
+		(at 99.06 35.56)
+		(uuid "cb39ce49-dc2e-52cf-9ae5-2fad794b9c0c")
+	)
+	(no_connect
+		(at 38.1 35.56)
+		(uuid "2c45bf1f-14d2-5a34-839d-dece52143315")
+	)
+	(no_connect
+		(at 38.1 38.1)
+		(uuid "03029999-8098-5e97-add5-bc4fb95371cc")
+	)
+	(no_connect
+		(at 38.1 43.18)
+		(uuid "59658b5e-4bf4-566d-b811-b0bf504a95d9")
+	)
+	(no_connect
+		(at 38.1 45.72)
+		(uuid "a4407bb3-9030-51e1-88f0-738765ce6334")
+	)
+	(no_connect
+		(at 38.1 50.8)
+		(uuid "15995150-d574-51ad-b24d-4ddbdb8a19b0")
+	)
+	(no_connect
+		(at 38.1 53.34)
+		(uuid "8fe68385-81e4-5057-aaaf-7839e45c385d")
+	)
 )

tools/retire_block.py

@@ -107,6 +107,25 @@ def sym_pin_coords(t, sym):
     px, py, rot = sym['at']
     return [xform(px, py, rot, sym['mirror'], lx, ly) for lx, ly, _ in lib_pins(t, sym['lib'])]
 
+def drop_sheet_spans(t, fname):
+    """Remove an entire (sheet ...) block by its Sheetfile property, plus any
+    (path ...) in (sheet_instances) referencing the sheet's UUID. Run on the parent
+    (root) sheet. Returns list of (start,end) spans to delete."""
+    spans = []
+    for m in re.finditer(r'\(sheet\b', t):
+        s = m.start(); e = paren_end(t, s); seg = t[s:e]
+        sf = re.search(r'Sheetfile"' + S + r'"([^"]+)"', seg)
+        if not sf or sf.group(1) != fname: continue
+        spans.append((s, e))
+        u = re.search(r'\(uuid' + S + r'"([0-9a-fA-F-]+)"', seg)
+        if u:
+            si = re.search(r'\(sheet_instances\b', t)
+            if si:
+                ss = si.start(); se = paren_end(t, ss)
+                for pm in re.finditer(r'\(path' + S + r'"[^"]*' + re.escape(u.group(1)) + r'[^"]*"', t[ss:se]):
+                    ps = ss + pm.start(); spans.append((ps, paren_end(t, ps)))
+    return spans
+
 def sheet_port_spans(t, names):
     """On a ROOT sheet, find (pin "NAME" ...) hierarchical ports inside (sheet ...) blocks
     whose name is in `names`. Returns (pin spans to remove, their connection coords)."""
@@ -128,6 +147,7 @@ def main():
     ap.add_argument('--nets', default='')
     ap.add_argument('--nc-pins', default='', help='module pin NUMBERS to no-connect (from analyzer regressions)')
     ap.add_argument('--sheet-ports', default='', help='hierarchical net names: remove matching sheet-symbol pins + connecting root wires (run on the ROOT sheet)')
+    ap.add_argument('--drop-sheet', default='', help='Sheetfile name: remove the whole (sheet ...) block + its sheet_instances path (run on the ROOT/parent sheet)')
     ap.add_argument('--module-lib', default='CM5IO:ComputeModule5-CM5')
     ap.add_argument('--apply', action='store_true')
     a = ap.parse_args()
@@ -191,6 +211,7 @@ def main():
     anchors = kept_pin_coords | kept_label_coords
     # sheet-symbol hierarchical ports to drop (root sheet) + their connection coords
     port_spans, port_coords = sheet_port_spans(t, port_names) if port_names else ([], set())
+    sheet_spans = drop_sheet_spans(t, a.drop_sheet) if a.drop_sheet else []
     seeds = set(removed_pin_coords) | set(retired_coords) | nc_coords | port_coords
 
     anchored_roots, seeded_roots = set(), set()
@@ -236,12 +257,13 @@ def main():
     print(f"retired-net labels: {len(retired_labels)} | wires removed (anchor-aware): {len(wire_remove)}")
     print(f"orphaned power flags: {len(power_spans)} | dangling NC removed: {len(dangling_nc)} | orphaned labels: {len(orphan_labels)}")
     if port_names: print(f"sheet-symbol ports removed: {len(port_spans)} ({sorted(port_names)})")
+    if a.drop_sheet: print(f"whole sheet dropped: {a.drop_sheet} ({len(sheet_spans)} block(s)/instance-path(s))")
     print(f"module pins to NC ({len(nc_pins)}): " + ", ".join(f"{n}@{xy}" for n, xy in nc_pins))
 
     # build new text: remove all spans, then append fresh no_connects on exposed module pins
     spans = sorted(set(sym_spans) | {(s, e) for s, e, _ in retired_labels}
                    | wire_remove_spans | set(power_spans) | set(dangling_nc) | set(orphan_labels)
-                   | set(port_spans), key=lambda x: -x[0])
+                   | set(port_spans) | set(sheet_spans), key=lambda x: -x[0])
     nt = t
     for s, e in spans:
         p = s