Strip PCIe-M2 (M-key/NVMe) sheet; re-baseline stripped carrier

Drops the unused M.2 M-key/NVMe block — design is 1x M.2 E-key (Wi-Fi)
only, since the CM5 exposes a single PCIe x1 lane (datasheet SC1466),
reserved for the E-key. The 10 freed PCIE_* lanes are NC on Module1
unit 2, to be rewired to a fresh E-key sheet in the add phase.

- CM5_HighSpeed: retire PCIE_* labels/wires, NC pins 102,104,106,109,
  110,112,116,118,122,124
- root CM5IO: drop whole PCIe-M2 (sheet) block; strip dangling PCIE_*
  pins off the kept CM5_HighSpeed sheet symbol
- delete carrier/PCIe-M2.kicad_sch; clean .kicad_pro sheets array + ERC
  exclusion
- retire_block.py: add --drop-sheet FILE (remove whole (sheet) block +
  sheet_instances path)
- analysis/baseline/carrier_stripped.json: new add-phase diff anchor

Verify: ERC 136->133 (zero new violation types); analyzer diff +0/~0
(cumulative -41 removed vs original ref); netlist confirms +5v/+3.3v/
GND/+1.8v intact (U8's M2_3v3 was a local rail, not board +3.3v).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

tools/retire_block.py

@@ -107,6 +107,25 @@ def sym_pin_coords(t, sym):
     px, py, rot = sym['at']
     return [xform(px, py, rot, sym['mirror'], lx, ly) for lx, ly, _ in lib_pins(t, sym['lib'])]
 
+def drop_sheet_spans(t, fname):
+    """Remove an entire (sheet ...) block by its Sheetfile property, plus any
+    (path ...) in (sheet_instances) referencing the sheet's UUID. Run on the parent
+    (root) sheet. Returns list of (start,end) spans to delete."""
+    spans = []
+    for m in re.finditer(r'\(sheet\b', t):
+        s = m.start(); e = paren_end(t, s); seg = t[s:e]
+        sf = re.search(r'Sheetfile"' + S + r'"([^"]+)"', seg)
+        if not sf or sf.group(1) != fname: continue
+        spans.append((s, e))
+        u = re.search(r'\(uuid' + S + r'"([0-9a-fA-F-]+)"', seg)
+        if u:
+            si = re.search(r'\(sheet_instances\b', t)
+            if si:
+                ss = si.start(); se = paren_end(t, ss)
+                for pm in re.finditer(r'\(path' + S + r'"[^"]*' + re.escape(u.group(1)) + r'[^"]*"', t[ss:se]):
+                    ps = ss + pm.start(); spans.append((ps, paren_end(t, ps)))
+    return spans
+
 def sheet_port_spans(t, names):
     """On a ROOT sheet, find (pin "NAME" ...) hierarchical ports inside (sheet ...) blocks
     whose name is in `names`. Returns (pin spans to remove, their connection coords)."""
@@ -128,6 +147,7 @@ def main():
     ap.add_argument('--nets', default='')
     ap.add_argument('--nc-pins', default='', help='module pin NUMBERS to no-connect (from analyzer regressions)')
     ap.add_argument('--sheet-ports', default='', help='hierarchical net names: remove matching sheet-symbol pins + connecting root wires (run on the ROOT sheet)')
+    ap.add_argument('--drop-sheet', default='', help='Sheetfile name: remove the whole (sheet ...) block + its sheet_instances path (run on the ROOT/parent sheet)')
     ap.add_argument('--module-lib', default='CM5IO:ComputeModule5-CM5')
     ap.add_argument('--apply', action='store_true')
     a = ap.parse_args()
@@ -191,6 +211,7 @@ def main():
     anchors = kept_pin_coords | kept_label_coords
     # sheet-symbol hierarchical ports to drop (root sheet) + their connection coords
     port_spans, port_coords = sheet_port_spans(t, port_names) if port_names else ([], set())
+    sheet_spans = drop_sheet_spans(t, a.drop_sheet) if a.drop_sheet else []
     seeds = set(removed_pin_coords) | set(retired_coords) | nc_coords | port_coords
 
     anchored_roots, seeded_roots = set(), set()
@@ -236,12 +257,13 @@ def main():
     print(f"retired-net labels: {len(retired_labels)} | wires removed (anchor-aware): {len(wire_remove)}")
     print(f"orphaned power flags: {len(power_spans)} | dangling NC removed: {len(dangling_nc)} | orphaned labels: {len(orphan_labels)}")
     if port_names: print(f"sheet-symbol ports removed: {len(port_spans)} ({sorted(port_names)})")
+    if a.drop_sheet: print(f"whole sheet dropped: {a.drop_sheet} ({len(sheet_spans)} block(s)/instance-path(s))")
     print(f"module pins to NC ({len(nc_pins)}): " + ", ".join(f"{n}@{xy}" for n, xy in nc_pins))
 
     # build new text: remove all spans, then append fresh no_connects on exposed module pins
     spans = sorted(set(sym_spans) | {(s, e) for s, e, _ in retired_labels}
                    | wire_remove_spans | set(power_spans) | set(dangling_nc) | set(orphan_labels)
-                   | set(port_spans), key=lambda x: -x[0])
+                   | set(port_spans) | set(sheet_spans), key=lambda x: -x[0])
     nt = t
     for s, e in spans:
         p = s