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Strip PCIe-M2 (M-key/NVMe) sheet; re-baseline stripped carrier

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Drops the unused M.2 M-key/NVMe block — design is 1x M.2 E-key (Wi-Fi)
only, since the CM5 exposes a single PCIe x1 lane (datasheet SC1466),
reserved for the E-key. The 10 freed PCIE_* lanes are NC on Module1
unit 2, to be rewired to a fresh E-key sheet in the add phase.

- CM5_HighSpeed: retire PCIE_* labels/wires, NC pins 102,104,106,109,
  110,112,116,118,122,124
- root CM5IO: drop whole PCIe-M2 (sheet) block; strip dangling PCIE_*
  pins off the kept CM5_HighSpeed sheet symbol
- delete carrier/PCIe-M2.kicad_sch; clean .kicad_pro sheets array + ERC
  exclusion
- retire_block.py: add --drop-sheet FILE (remove whole (sheet) block +
  sheet_instances path)
- analysis/baseline/carrier_stripped.json: new add-phase diff anchor

Verify: ERC 136->133 (zero new violation types); analyzer diff +0/~0
(cumulative -41 removed vs original ref); netlist confirms +5v/+3.3v/
GND/+1.8v intact (U8's M2_3v3 was a local rail, not board +3.3v).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
noise
2026-06-30 11:27:41 -04:00
parent 6082613e88
commit 1d169476fb
7 changed files with 70945 additions and 8512 deletions
Download Patch File Download Diff File Expand all files Collapse all files

349
carrier/CM5IO.kicad_sch
View File

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(uuid "7aaa8496-fa91-4cdd-a95c-0fb4934a563f")
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(wire
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(uuid "b38f69e2-7f84-451a-9316-b038cdf98445")
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(wire
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(uuid "e83e0227-ac0f-4180-82bd-68d3a7b56476")
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(wire
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@@ -1539,16 +1449,6 @@
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(uuid "f1f3a160-e530-44d2-9a4b-2d9f99bce435")
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(wire
(pts
(xy 186.69 76.2) (xy 214.63 76.2)
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(stroke
(width 0)
(type default)
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(uuid "fa92842d-37e8-4687-b4f4-0cfd415b8d84")
)
(text "Connectors\n-------\nEthernet\nSDCARD\n40way RPI\nJumpers\nFan\nBattery"
(exclude_from_sim no)
(at 150.876 147.066 0)
@@ -3521,86 +3421,6 @@
)
(uuid "0f22151c-f260-4674-b486-4710a2c42a55")
)
(pin "PCIE_CLK_P" output
(at 186.69 57.15 0)
(effects
(font
(size 1.27 1.27)
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(justify right)
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(uuid "fe8d9267-7834-48d6-a191-c8724b2ee78d")
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(pin "PCIE_CLK_N" output
(at 186.69 59.69 0)
(effects
(font
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(justify right)
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(uuid "0b21a65d-d20b-411e-920a-75c343ac5136")
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(pin "PCIE_TX_P" output
(at 186.69 43.18 0)
(effects
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(justify right)
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(uuid "3cd1bda0-18db-417d-b581-a0c50623df68")
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(pin "PCIE_TX_N" output
(at 186.69 45.72 0)
(effects
(font
(size 1.27 1.27)
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(justify right)
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(uuid "d57dcfee-5058-4fc2-a68b-05f9a48f685b")
)
(pin "PCIE_nRST" output
(at 186.69 64.77 0)
(effects
(font
(size 1.27 1.27)
)
(justify right)
)
(uuid "03c52831-5dc5-43c5-a442-8d23643b46fb")
)
(pin "PCIE_RX_P" input
(at 186.69 50.8 0)
(effects
(font
(size 1.27 1.27)
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(justify right)
)
(uuid "a1823eb2-fb0d-4ed8-8b96-04184ac3a9d5")
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(pin "PCIE_RX_N" input
(at 186.69 53.34 0)
(effects
(font
(size 1.27 1.27)
)
(justify right)
)
(uuid "29e78086-2175-405e-9ba3-c48766d2f50c")
)
(pin "PCIE_nCLKREQ" input
(at 186.69 68.58 0)
(effects
(font
(size 1.27 1.27)
)
(justify right)
)
(uuid "94a873dc-af67-4ef9-8159-1f7c93eeb3d7")
)
(pin "+3.3v" input
(at 129.54 76.2 180)
(effects
@@ -3631,26 +3451,6 @@
)
(uuid "9bb20359-0f8b-45bc-9d38-6626ed3a939d")
)
(pin "PCIE_PWR_EN" output
(at 186.69 72.39 0)
(effects
(font
(size 1.27 1.27)
)
(justify right)
)
(uuid "e445000d-94a3-4ed1-b023-6aae972d0a39")
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(pin "PCIE_nWAKE" input
(at 186.69 76.2 0)
(effects
(font
(size 1.27 1.27)
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(justify right)
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(uuid "31cb0f66-393a-491f-95aa-c50644299a5d")
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(instances
(project "CM5IO"
(path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55"
@@ -3659,155 +3459,6 @@
)
)
)
(sheet
(at 214.63 34.29)
(size 27.94 52.07)
(fields_autoplaced yes)
(stroke
(width 0.152)
(type solid)
(color 132 0 132 1)
)
(fill
(color 255 255 255 0.0000)
)
(uuid "00000000-0000-0000-0000-00005ed4bb5b")
(property "Sheetname" "PCIe-M2"
(at 214.63 33.5786 0)
(effects
(font
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(justify left bottom)
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(property "Sheetfile" "PCIe-M2.kicad_sch"
(at 214.63 86.9444 0)
(effects
(font
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(justify left top)
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)
(pin "PCIE_CLK_P" input
(at 214.63 57.15 180)
(effects
(font
(size 1.27 1.27)
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(justify left)
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(uuid "ee27d19c-8dca-4ac8-a760-6dfd54d28071")
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(pin "PCIE_CLK_N" input
(at 214.63 59.69 180)
(effects
(font
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(justify left)
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(uuid "9b0a1687-7e1b-4a04-a30b-c27a072a2949")
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(pin "PCIE_TX_P" input
(at 214.63 43.18 180)
(effects
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(justify left)
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(uuid "c01d25cd-f4bb-4ef3-b5ea-533a2a4ddb2b")
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(pin "PCIE_TX_N" input
(at 214.63 45.72 180)
(effects
(font
(size 1.27 1.27)
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(justify left)
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(uuid "9e1b837f-0d34-4a18-9644-9ee68f141f46")
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(pin "PCIE_nCLKREQ" output
(at 214.63 68.58 180)
(effects
(font
(size 1.27 1.27)
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(justify left)
)
(uuid "63ff1c93-3f96-4c33-b498-5dd8c33bccc0")
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(pin "PCIE_nRST" input
(at 214.63 64.77 180)
(effects
(font
(size 1.27 1.27)
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(justify left)
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(uuid "b88717bd-086f-46cd-9d3f-0396009d0996")
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(pin "PCIE_RX_P" output
(at 214.63 50.8 180)
(effects
(font
(size 1.27 1.27)
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(justify left)
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(uuid "61fe293f-6808-4b7f-9340-9aaac7054a97")
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(pin "PCIE_RX_N" output
(at 214.63 53.34 180)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
(uuid "2f215f15-3d52-4c91-93e6-3ea03a95622f")
)
(pin "+5v" input
(at 242.57 64.77 0)
(effects
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(justify right)
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(uuid "0217dfc4-fc13-4699-99ad-d9948522648e")
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(pin "PCIE_PWR_EN" input
(at 214.63 72.39 180)
(effects
(font
(size 1.27 1.27)
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(justify left)
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(uuid "97775b76-6935-4c0f-9fc9-91db55c7f4d2")
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(pin "PCIE_nWAKE" output
(at 214.63 76.2 180)
(effects
(font
(size 1.27 1.27)
)
(justify left)
)
(uuid "29caf48f-b190-47ea-a0b4-a078d43caa04")
)
(instances
(project "CM5IO"
(path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55"
(page "4")
)
)
)
)
(sheet_instances
(path "/"
(page "1")