Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes

First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).

- PCIe link-0 wired to the 9 freed CM5 pins via global labels
  (TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
  corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
  (106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
  pins + by-name labels; grid-snap; cross-connector ERC pin retyping)

Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.

Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

carrier/CM5_HighSpeed.kicad_sch

@@ -12684,44 +12684,62 @@
 		(at 38.1 144.78)
 		(uuid "3e94757c-62b4-5b7d-9eb9-0bce1d18da64")
 	)
-	(no_connect
-		(at 38.1 25.4)
-		(uuid "aab94d9f-4d88-55fd-8963-e421713879b9")
-	)
-	(no_connect
-		(at 38.1 27.94)
-		(uuid "bf767c9b-22d7-5638-8a4e-bb8fee0ab324")
-	)
 	(no_connect
 		(at 38.1 30.48)
 		(uuid "22043a85-7370-5a2b-9195-7034c3f95e65")
 	)
-	(no_connect
-		(at 99.06 35.56)
-		(uuid "cb39ce49-dc2e-52cf-9ae5-2fad794b9c0c")
+	(global_label "PCIE_nCLKREQ"
+		(shape input)
+		(at 38.1 25.4 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "2d6bcc7f-bf6a-5023-b9a8-f27291d2d3ae")
 	)
-	(no_connect
-		(at 38.1 35.56)
-		(uuid "2c45bf1f-14d2-5a34-839d-dece52143315")
+	(global_label "PCIE_nWAKE"
+		(shape input)
+		(at 38.1 27.94 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "d8b40857-196b-5180-bd8c-a975b3ad79da")
 	)
-	(no_connect
-		(at 38.1 38.1)
-		(uuid "03029999-8098-5e97-add5-bc4fb95371cc")
+	(global_label "PCIE_nRST"
+		(shape input)
+		(at 99.06 35.56 0)
+		(effects (font (size 1.27 1.27)) (justify left))
+		(uuid "2274596d-a153-5b0c-816c-fd4b3c161cd2")
 	)
-	(no_connect
-		(at 38.1 43.18)
-		(uuid "59658b5e-4bf4-566d-b811-b0bf504a95d9")
+	(global_label "PCIE_CLK_P"
+		(shape input)
+		(at 38.1 35.56 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "e43761cd-21a8-5c71-9bd0-14fa2388618a")
 	)
-	(no_connect
-		(at 38.1 45.72)
-		(uuid "a4407bb3-9030-51e1-88f0-738765ce6334")
+	(global_label "PCIE_CLK_N"
+		(shape input)
+		(at 38.1 38.1 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "cee20a9f-240d-5034-a7d9-e0ea94c6b19e")
 	)
-	(no_connect
-		(at 38.1 50.8)
-		(uuid "15995150-d574-51ad-b24d-4ddbdb8a19b0")
+	(global_label "PCIE_RX_P"
+		(shape input)
+		(at 38.1 43.18 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "dbc3aa3a-3d74-54a7-8e16-45a47db880db")
 	)
-	(no_connect
-		(at 38.1 53.34)
-		(uuid "8fe68385-81e4-5057-aaaf-7839e45c385d")
+	(global_label "PCIE_RX_N"
+		(shape input)
+		(at 38.1 45.72 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "257305aa-6458-525c-be07-f4457a28ba77")
+	)
+	(global_label "PCIE_TX_P"
+		(shape input)
+		(at 38.1 50.8 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "ac99503c-1d9e-5ff9-a810-1a99c646684d")
+	)
+	(global_label "PCIE_TX_N"
+		(shape input)
+		(at 38.1 53.34 180)
+		(effects (font (size 1.27 1.27)) (justify right))
+		(uuid "1273b5e1-2d9d-5d45-bc25-040dc4ddc6f1")
 	)
 )