Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes

First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).

- PCIe link-0 wired to the 9 freed CM5 pins via global labels
  (TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
  corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
  (106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
  pins + by-name labels; grid-snap; cross-connector ERC pin retyping)

Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.

Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

carrier/CM5IO.kicad_sch

@@ -3459,6 +3459,16 @@
 			)
 		)
 	)
+	(sheet
+		(at 205 34.29)
+		(size 30 20)
+		(stroke (width 0.1524) (type solid) (color 132 0 132 1))
+		(fill (color 255 255 255 0.0000))
+		(uuid "c57f5f03-e2c5-5c1b-ba90-8072a2a088a0")
+		(property "Sheetname" "M2_Ekey" (at 205 30.48 0) (effects (font (size 1.27 1.27)) (justify left bottom)))
+		(property "Sheetfile" "M2_Ekey.kicad_sch" (at 205 31.75 0) (effects (font (size 1.27 1.27)) (justify left top)))
+		(instances (project "CM5IO" (path "/e63e39d7-6ac0-4ffd-8aa3-1841a4541b55" (page "4"))))
+	)
 	(sheet_instances
 		(path "/"
 			(page "1")