Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes

First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).

- PCIe link-0 wired to the 9 freed CM5 pins via global labels
  (TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
  corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
  (106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
  pins + by-name labels; grid-snap; cross-connector ERC pin retyping)

Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.

Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

PORT_STATUS.md

@@ -84,10 +84,22 @@ Notes that bit us (don't re-learn the hard way):
 ## Next steps
 
 1. ~~Drop the PCIe-M2 sheet entirely~~ **DONE** (see strip table). Confirmed E-key-only (no M-key SSD).
-2. **Re-baseline**: capture a new analyzer baseline of `carrier/` so the add phase diffs against the
-   stripped design, not the original reference. (`analyze_schematic.py carrier/CM5IO.kicad_sch -o analysis/baseline/carrier_stripped.json`)
-3. **Add phase**: 15V→5V buck front-end (reverse-protection + TVS), M.2 E-key (PCIe Gen2 ×1 +
-   CLKREQ/PERST/RF_KILL + 3.3V), GPS connector, PPS distribution (GPS PPS → TVS → Schmitt buffer →
+2. ~~Re-baseline~~ **DONE** — `analysis/baseline/carrier_stripped.json` is the add-phase diff anchor.
+3. **M.2 E-key sheet** ✅ **DONE** (`carrier/M2_Ekey.kicad_sch`, generated by `tools/build_ekey.py`).
+   J_E = KiCad `Connector:Bus_M.2_Socket_E`, fp `Connector_PCBEdge:M.2_2230-xx-E`. PCIe link-0 wired to the
+   9 freed CM5 pins via **global labels** (PCIE_TX/RX/CLK ±, nRST, nCLKREQ, nWAKE — netlist-confirmed J_E↔Module1);
+   `+3V3_RF` (4 pins) + 10µF∥2×0.1µF decoupling + temp PWR_FLAG; 11 GND; W_DISABLE1/2 10k pull-ups to +3V3_RF;
+   ~41 NC (USB/BT, PCM/I2S, SDIO, UART, COEX, I2C, link-1). RX **not** coupled on carrier (card-side per M.2; BOM C_PCIE removed).
+   **Verify:** ERC 133→133 (zero new); analyzer diff +7 added, **0 regressions**.
+   Connector-symbol pin types remodeled for cross-connector ERC: lines CM5 drives → `passive`; lines the card
+   drives into CM5 inputs (RX pair + CLKREQ#/WAKE#) → `output`.
+   **Open items (review/next):** (a) CM5 `PCIE_PWR_EN` (pin 106) still NC — wire to the +3V3_RF buck EN in the
+   power sheet; (b) the temp PWR_FLAG on +3V3_RF must be REMOVED once the buck drives it (else dual-driver ERC);
+   (c) optionally route `WIFI_DISABLE#` to a CM5 GPIO for SW radio control; (d) analyzer CG-AUD 5:1 sig/gnd on J_E
+   is inherent to the M.2 connector (INFO, not fixable). New tool: `tools/build_ekey.py` (place connector + auto-NC + labels).
+4. **Remaining add phase**: 15V→5V buck front-end (reverse-protection + TVS); the two 3.3V rails
+   (`+3V3_RF` for the E-key — wire its buck EN to CM5 `PCIE_PWR_EN`/106 and drop the temp PWR_FLAG —
+   and `+3V3_AUX` for GPS/IO); GPS connector; PPS distribution (GPS PPS → TVS → Schmitt buffer →
    fan-out: CM5 `Ethernet_SYNC_OUT` + 2 header taps). SPICE-validate the buck divider + PPS network.
 
 ## Out-of-repo notes