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Add M.2 E-key (Wi-Fi) sheet; wire PCIe x1 to freed CM5 lanes

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First add-phase block. New carrier/M2_Ekey.kicad_sch (generated by
tools/build_ekey.py) places J_E = Connector:Bus_M.2_Socket_E
(fp Connector_PCBEdge:M.2_2230-xx-E) for an AsiaRF AW7915 / MT7915
Wi-Fi card. Reuses the single CM5 PCIe x1 Gen2 lane freed by the
PCIe-M2 drop (design confirmed E-key-only, no M-key SSD).

- PCIe link-0 wired to the 9 freed CM5 pins via global labels
  (TX/RX/CLK +/-, nRST, nCLKREQ, nWAKE) - netlist-confirmed J_E<->Module1
- +3V3_RF (pins 2/4/72/74) + 10uF||2x0.1uF decoupling + temp PWR_FLAG
- W_DISABLE1/2 10k pull-ups; 11 GND; ~41 NC (USB/BT, SDIO, UART, etc.)
- RX NOT AC-coupled on carrier (card supplies TX coupling per M.2 spec);
  corrected Pinout_BOM, dropped C_PCIE
- CM5_HighSpeed: replaced the 9 PCIe-pin NC markers with global labels
  (106/PCIE_PWR_EN stays NC, reserved for the +3V3_RF buck EN)
- root + .kicad_pro: registered the M2_Ekey sub-sheet
- tools/build_ekey.py: new generator (place connector + auto-NC unused
  pins + by-name labels; grid-snap; cross-connector ERC pin retyping)

Verify: ERC 133->133 (zero new violations); analyzer diff +7 added,
0 regressions; netlist confirms all 9 PCIe nets span J_E and Module1.

Open (power phase): wire PCIE_PWR_EN->buck EN, drop temp PWR_FLAG once
the +3V3_RF buck drives the rail.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
noise
2026-06-30 14:58:09 -04:00
parent 1d169476fb
commit 18ef98a88e
7 changed files with 2650 additions and 37 deletions
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6
CM5_Carrier_Pinout_BOM.md
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@@ -94,7 +94,7 @@ A+E key edge. Populate PCIe + control; leave USB pins NC.
| CLKREQ0# | PCIE_CLKREQ# | CM5 PCIe CLKREQ |
| REFCLK+ / REFCLK− | PCIE_REFCLK_P/N | CM5 PCIe refclk (100 MHz) |
| PETp0/PETn0 | PCIE_TX_P/N | CM5 PCIe TX (AC-coupled on CM5) |
| PERp0/PERn0 | PCIE_RX_P/N | CM5 PCIe RX (AC-couple caps on carrier) |
| PERp0/PERn0 | PCIE_RX_P/N | CM5 PCIe RX (**direct** — card supplies its own TX coupling per M.2; no carrier caps) |
| W_DISABLE1# (RF_KILL) | WIFI_DISABLE# | pull-up + optional GPIO |
| 3.3 V pins | +3V3_RF | from 15→3.3 V 4 A RF buck (direct) |
| GND | GND | |
@@ -221,7 +221,7 @@ PoE pins of the magjack: leave **unloaded / NC** (no PoE in this design).
| 6 | J_ETH | 1 | RJ45 1:1 GbE magjack | Pulse JXD0-0001NL / Bel V890-1AX | 2–4 |
| 7 | ESD_ETH | 1 | Ethernet ESD array | TI TPD4E1U06 / Bourns | 0.3–0.6 |
| 8 | J_E | 1 | M.2 E-key (A+E) 2230 conn + standoff | Amphenol/Attend 119A-92A00 | 1.2–2 |
| 9 | C_PCIE | 4 | PCIe RX AC-couple 0.1 µF | GRM 0402 100 nF | 0.05 |
| ~~9~~ | ~~C_PCIE~~ | 0 | **REMOVED** — PCIe RX coupling lives on the M.2 card's TX (standard M.2); CM5 couples its own TX. No carrier caps. | — |
| 10 | J_USB1/2 | 2 | USB-A USB3.0 right-angle | Amphenol UE27AC54100 | 0.8–1.4 ea |
| 11 | J_UPROG | 1 | USB-C 16-pin (USB2 + CC) | GCT USB4085 | 0.5–1 |
| 12 | ESD_USB | 3 | USB ESD array | ST USBLC6-2SC6 | 0.15 ea |
@@ -267,7 +267,7 @@ DF40 pair (line 1) = ~45–60% of BOM. Everything else commodity.
1. Import CM5 KiCad symbol from `refs/CM5IO.kicad_sym` — pin map is now resolved in `CM5_Carrier_PinMap.md` (all 200 pins).
2. **SYNC (pin 18) is 3.3 V** — drive directly from the Schmitt via a series R; **no level translator** (corrected).
3. AC-couple PCIe **RX** on carrier (TX coupled on CM5).
3. PCIe **RX is NOT coupled on the carrier** — caps live on the M.2 card's TX (standard M.2); CM5 couples its own TX. (Corrected: earlier text/BOM said carrier-side; double-coupling would break the link.)
4. CC 5.1 kΩ pulldowns on USB-C; nRPIBOOT jumper logic.
5. Magjack PoE pins NC; Bob-Smith + ESD on cable side.
6. Both 15→3.3 buck inductors/thermals sized for their rails (RF 4 A, AUX 1 A); all bucks rated ≥20 V Vin, low-duty-capable.