Power stage 4: TPS54202 15V->+3V3_AUX 1A quiet-rail buck (power sheet complete)

- TPS54202 SOT-23-6 sync, fixed 500kHz; custom symbol CM5IO:TPS54202 (KiCad
  lib symbol extends TPS54302 with no own pins, cannot embed standalone)
- Abs-max gate: VIN 30V vs SMBJ18A clamp <=29.2V at rated surge (0.8V margin,
  transient-only) - documented, passed
- FB 100k/22.1k + 56pF Cff per TI 3.3V table -> 3.29V (SPICE: vfb 0.597V,
  inrush settles 3.315V); L 10uH, Cout 2x22uF/16V
- EN abs-max 7V -> UVLO divider 866k/110k from VIN_PROT (start 10.13V /
  stop 8.61V, EN ~1.9V at 15V); no direct VIN tie
- Renamed input cap C_IN33A -> C_IN33Aa: SPICE names are case-insensitive and
  collided with stage-3 C_IN33a, silently skipping the VIN_PROT decoupling sim
- Verify: ERC 133->133 zero new; analyzer +65/-0 zero regressions;
  SPICE 23 pass / 2 benign warn / 0 fail / 0 skip

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

PORT_STATUS.md

@@ -7,22 +7,23 @@
 ## ▶ RESUME HERE (session handoff, 2026-07-01)
 
 **State:** branch `port/strip-phase`. Sheets in `carrier/`: root `CM5IO`, `CM5_GPIO`,
-`CM5_HighSpeed` (reference, stripped), `M2_Ekey` (E-key, done), `Power` (stages 1–3 done).
-Baseline anchor: `analysis/baseline/carrier_stripped.json`.
+`CM5_HighSpeed` (reference, stripped), `M2_Ekey` (E-key, done), `Power` (**stages 1–4 done —
+power sheet complete**). Baseline anchor: `analysis/baseline/carrier_stripped.json`.
 
 **Done:** strip phase (microSD/HDMI/MIPI/PCIe-M2); M.2 E-key sheet (PCIe ×1 to CM5); Power
 stage 1 (LM74700 ideal-diode input protection → `VIN_PROT`); Power stage 2 (LM61460-Q1
-15→`+5v` 5 A sync buck, SPICE-verified 5.02 V); Power stage 3 (LM61460-Q1 15→`+3V3_RF` 4 A,
-SPICE-verified 3.32 V; EN ← CM5 `PCIE_PWR_EN`/106 + 100k pull-down like reference R14; E-key
-temp PWR_FLAG removed — buck is the sole `+3V3_RF` driver). Current whole-design **ERC = 133**
-(all pre-existing types; a good edit adds **zero new**).
+15→`+5v` 5 A, SPICE 5.02 V); Power stage 3 (LM61460-Q1 15→`+3V3_RF` 4 A, SPICE 3.32 V; EN ←
+CM5 `PCIE_PWR_EN`/106 + 100k pull-down); Power stage 4 (TPS54202 15→`+3V3_AUX` ~1 A, SPICE
+3.315 V; UVLO divider start 10.1 V / stop 8.6 V). Current whole-design **ERC = 133** (all
+pre-existing types; a good edit adds **zero new**).
 
-**NEXT ACTION → Power Stage 4: `U_BUCK33A` 15→`+3V3_AUX` ~1 A.** Candidate part TPS54202
-(28 V sync) — datasheet-verify first (KiCad has `Regulator_Switching:TPS54202DDC`). One check
-that MUST pass: the SMBJ18A clamp (~29 V at rated Ipp) vs the part's VIN abs-max — if the
-datasheet says <30 V abs-max, pick a 36 V-class sync part instead (LMR51430/TPS54360-class)
-or justify why the surge case is acceptable. FB divider per that part's VREF; SPICE-verify.
-`+3V3_AUX` is a NEW net → **global** label. Then the GPS + PPS sheet, then power-budget review.
+**NEXT ACTION → GPS + PPS distribution sheet** (last new block, see step 5 below): GPS
+connector (PPS + UART + 3V3 + GND, powered from `+3V3_AUX`); PPS → TVS → Schmitt buffer
+(LVC1G17 @ 3.3 V) → fan-out: CM5 `Ethernet_SYNC_OUT` (J2 pin-6 net, no translator) + 2 header
+taps. Reuse the build_*.py generator pattern (new `tools/build_gps.py` or extend build_power).
+UART: decide which CM5 UART pins to use (check `CM5_GPIO` — reserve/label; datasheet is the
+authority). After that: whole-power-tree budget review, then hygiene pass (title blocks, refdes
+numbering — note generated refs like `J_E`/`J_PWR` trip kicad-cli's "annotation errors" warning).
 
 **How to build/verify (every change):**
 - Sheets are generated wholesale — edit `tools/build_ekey.py` / `tools/build_power.py`, then
@@ -133,7 +134,7 @@ Notes that bit us (don't re-learn the hard way):
    - **Stage 1 — input protection ✅ DONE.** J_PWR(15V) → D_REV `LM74700-Q1` ideal-diode + Q_REV N-FET (reverse-polarity/-current) → `VIN_PROT`; `SMBJ18A` TVS + 100µF/25V ∥ 10µF/50V bulk; C_VCAP charge-pump cap. Netlist-verified topology; ERC 133→133 (zero new); analyzer 0 regressions. **Confirm vs LM74700-Q1 datasheet:** C_VCAP value, EN-to-+15V_IN, FET pick (Vds≥30V, SOA/inrush) + optional gate R.
    - **Stage 2 — U_BUCK5 15→`+5v` 5A ✅ DONE.** `LM61460-Q1` (6A, 42V absmax sync; **custom symbol built from the datasheet** → `carrier/CM5IO.kicad_sym` as `CM5IO:LM61460-Q1`, fp `Package_SO:Texas_HTSSOP-14-1EP…ThermalVias`). VREF=1.0V → FB divider R_FBT5 40.2k / R_FBB5 10.0k = **5.02V (SPICE-confirmed vfb=1.0V)**. L5 4.7µH, Cout 2×47µF/16V, Cin 2×10µF/50V, Cboot 100n+Rboot 4.7Ω, RT 31.6k(~400kHz), BIAS→+5v, EN→VIN_PROT, PGOOD 100k→+5v. **`+5v` kept HIERARCHICAL** (pre-existing carrier net; global would collide `same_local_global_label`) — Power sheet exposes a `+5v` sheet pin, tied into the root `+5v` net; netlist-verified it drives Module1 + GPIO + USB. ERC 133→133 (zero new); analyzer +32 added **0 regressions**; SPICE 12/13 pass, 1 benign warn (L5/Cboot mis-detected as LC filter). **Confirm vs datasheet:** RT freq, L sat ≥7A, EP=pad15, optional EN UVLO divider.
    - **Stage 3 — U_BUCK33R 15→`+3V3_RF` 4A ✅ DONE.** Second `LM61460-Q1` (shared BOM with stage 2: L 4.7µH/7A ripple ~1.3A=33%, Cin 2×10µ/50V, Cout 2×47µ/16V, RT 31.6k ~420kHz, Cboot 100n+Rboot 4.7). FB divider R_FBT33 23.2k / R_FBB33 10.0k = **3.32V (SPICE: vfb 0.994V, inrush settles 3.32V)**. BIAS→`+3V3_RF` (datasheet: valid ≥3.1V, auto-falls back to VIN below). **EN ← CM5 `PCIE_PWR_EN`** (Module1 pin 106: NC swapped for a global label on `CM5_HighSpeed`) + **R_EN33 100k pull-down** (mirrors reference R14 — netlist-verified `Module1.106 + U_BUCK33R.7 + R_EN33.1`) so the Wi-Fi rail is OFF until the CM5 asserts it. **E-key temp `#FLG33RF` PWR_FLAG removed** (build_ekey); the buck's PWR_FLAG on L33.2 is now the sole `+3V3_RF` driver — netlist shows buck + all 4 J_E power pins + pull-ups + decoupling on one net. Verify: ERC 133→133 zero new; analyzer +49 added **0 regressions**; SPICE 17 pass / 2 benign warn (the L/C_BOOT "LC filter" mis-detect, once per buck) / 0 fail. (Note: `kicad-cli` netlist export prints a pre-existing "annotation errors" warning — un-numbered generated refdeses like `J_E`/`J_PWR`; present at fd627f5 too, cosmetic.)
-   - **Stage 4** U_BUCK33A 15→3.3V ~1A → `+3V3_AUX`. SPICE-validate the feedback divider (see NEXT ACTION above for the part-selection gate).
+   - **Stage 4 — U_BUCK33A 15→`+3V3_AUX` ~1A ✅ DONE (power sheet complete).** `TPS54202` (SOT-23-6, sync, fixed 500kHz, VFB=0.596V). **Abs-max gate PASSED but thin:** VIN abs-max **30V** vs SMBJ18A clamp ≤29.2V at full rated 600W surge → 0.8V transient margin (operating max 28V is not the surge number). Custom symbol `CM5IO:TPS54202` (the KiCad lib symbol `extends TPS54302` — no own pins, can't embed standalone) + bare copy in `carrier/CM5IO.kicad_sym`. FB per TI's 3.3V table row: **100k/22.1k + Cff 56pF → 3.29V (SPICE: vfb 0.597V, inrush settles 3.315V)**. L 10µH/2.5A (ΔI~0.52A), Cout 2×22µF/16V, Cboot 100n, Cin 10µF/50V+100n. **EN abs-max is only 7V → NO direct VIN tie** (unlike LM61460): UVLO divider **866k/110k** (solved from Ip=0.7µA/Ih=1.55µA, VEN 1.21/1.19V) → **start 10.13V / stop 8.61V**, EN ~1.9V at 15V in (~3.5V at 29V clamp — safe). FB+EN pins typed `passive` (divider-only nets). Verify: ERC 133→133 zero new; analyzer +65/−0 zero regressions (warn/error set identical to stage 3); SPICE 23 pass / 2 benign warn / 0 fail / 0 skip. **New tooling gap found:** `simulate_subcircuits.py` lowercases refdeses into SPICE names — `C_IN33A` vs stage-3 `C_IN33a` collided ("device already exists") and silently SKIPPED the whole VIN_PROT decoupling group → renamed to `C_IN33Aa`. Rule: **never create refdeses differing only by case.**
 5. **GPS + PPS distribution**: GPS connector (PPS+UART+3V3+GND); PPS → TVS → Schmitt (LVC1G17) →
    fan-out: CM5 `Ethernet_SYNC_OUT` (J2 pin-6 net, 3.3V, no translator) + 2 header taps. SPICE/timing check.