Files
SequencerIO/arnold/__pycache__/config.cpython-311.pyc

132 lines
28 KiB
Plaintext
Raw Normal View History

2026-03-02 17:48:55 -05:00
<EFBFBD>
<00><01>iL<00><01><><00>dZddlmZddlZddlmZmZddlmZddl m
Z
ddl m Z m Z mZmZeGd <09>d
<EFBFBD><00><00><00>ZeGd <0B>d <0C><00><00><00>ZeGd <0A>d<0E><00><00><00>ZeGd<0F>d<10><00><00><00>ZeGd<11>d<12><00><00><00>ZeGd<13>d<14><00><00><00>ZGd<15>de<16><00>Zd8d<1D>Zd9d <20>Zd:d$<24>Zd;d'<27>Zd<d+<2B>Zd=d/<2F>Zd>d1<64>Zd?d6<64>Zd@d7<64>Z dS)AuM
arnold/config.py — YAML config loader, dataclasses, and validation.
Schema:
devices: list of EBC100 controllers
logical_io: named signals mapped to device/slot/point
sequences: ordered step lists with timing and actions
Address spaces (EBC100 hardware):
The T1H-EBC100 maintains TWO independent Modbus address spaces:
coil space (1-bit) — digital modules (inputs + outputs + relays)
FC01 read coils, FC02 read discrete inputs,
FC05 write single coil, FC15 write multiple coils
Flat sequential addressing by physical slot order.
register space (16-bit) — analog + temperature modules
FC03 read holding registers, FC04 read input registers,
FC06 write single register, FC16 write multiple registers
Flat sequential addressing by physical slot order,
INDEPENDENT of coil space.
A digital module in slot 1 advances coil_offset but not register_offset.
An analog module in slot 2 advances register_offset but not coil_offset.
<EFBFBD>)<01> annotationsN)<02> dataclass<73>field)<01>Path)<01>Literal<61>)<04>MODULE_REGISTRY<52>
ModuleType<EFBFBD>Category<72>get_module_typec<01>Z<00>eZdZUded<ded<ded<ded<ded <d
ed <d Zded <dS)<0F> ModuleConfig<69>int<6E>slot<6F>str<74>typer
<00> module_type<70>pointsr <00>category<72>Literal['coil', 'register']<5D> modbus_spacer<00>modbus_addressN)<05>__name__<5F>
__module__<EFBFBD> __qualname__<5F>__annotations__r<00><00><00>(/home/noise/Code/arnold/arnold/config.pyrr)sd<00><00><00><00><00><00><00> <0A>I<EFBFBD>I<EFBFBD>I<EFBFBD> <0A>I<EFBFBD>I<EFBFBD>I<EFBFBD><1B><1B><1B><1B><0F>K<EFBFBD>K<EFBFBD>K<EFBFBD><16><16><16><16>-<2D>-<2D>-<2D>-<2D><1C>N<EFBFBD><1B><1B><1B><1B><1B>rrc<01><><00>eZdZUded<ded<ded<ded<ded<ee<05><08><00>Zd ed
<dd<0E>Zdd<0F>Zdd<10>Z dd<11>Z
dd<12>Z dd<13>Z dd<14>Z dd<15>Zdd<16>Zdd<17>Zdd<18>ZdS)<1D> DeviceConfigr<00>id<69>hostr<00>port<72>unit_id<69>poll_interval_ms<6D><01>default_factory<72>list[ModuleConfig]<5D>modulesr<00>return<72>ModuleConfig | Nonec<01>F<00><01>t<00>fd<01>|jD<00><00>d<00><00>S)Nc3<01>2<00>K<00>|]}|j<00>k<00> |V<00><00>dS<00>N<>r)<03>.0<EFBFBD>mrs <20>r<00> <genexpr>z/DeviceConfig.module_for_slot.<locals>.<genexpr>@s)<00><><00><00><00>?<3F>?<3F>1<EFBFBD><01><06>$<24><0E><0E>Q<EFBFBD><0E><0E><0E><0E>?<3F>?r)<02>nextr*)<02>selfrs `r<00>module_for_slotzDeviceConfig.module_for_slot?s*<00><><00><13>?<3F>?<3F>?<3F>?<3F><04> <0C>?<3F>?<3F>?<3F><14>F<>F<>Frc<01>$<00>d<01>|jD<00><00>S)Nc<01>(<00>g|]}|jdk<00> |<01><02>S)<01> digital_input<75>r<00>r1r2s r<00>
<listcomp>z6DeviceConfig.digital_input_modules.<locals>.<listcomp>E<00>.<00><00>2<>2<>2<>a<EFBFBD><14>:<3A><1F>0<>0<><12>0<>0<>0r<00>r*<00>r5s r<00>digital_input_modulesz"DeviceConfig.digital_input_modulesD<00>$<00><00>2<>2<>4<EFBFBD><<3C>2<>2<>2<> 2rc<01>$<00>d<01>|jD<00><00>S)Nc<01>$<00>g|] }|jdv<00> |<01><02>S))<02>digital_output<75> relay_outputr:r;s rr<z7DeviceConfig.digital_output_modules.<locals>.<listcomp>Is2<00><00>E<01>E<01>E<01>a<EFBFBD><14>:<3A>!C<>C<>C<><12>C<>C<>Crr>r?s r<00>digital_output_modulesz#DeviceConfig.digital_output_modulesHs*<00><00>E<01>E<01>4<EFBFBD><<3C>E<01>E<01>E<01> Erc<01>X<00>td<01>|<00><00><00>D<00><00><00><00>S)z/Total discrete input bits (for FC02 bulk read).c3<01>$K<00>|] }|jV<00><00> dSr/<00>rr;s rr3z2DeviceConfig.total_input_points.<locals>.<genexpr>N<00>$<00><00><00><00>B<>B<><01>1<EFBFBD>8<EFBFBD>B<>B<>B<>B<>B<>Br)<02>sumr@r?s r<00>total_input_pointszDeviceConfig.total_input_pointsL<00>+<00><00><12>B<>B<>T<EFBFBD>%?<3F>%?<3F>%A<>%A<>B<>B<>B<>B<>B<>Brc<01>X<00>td<01>|<00><00><00>D<00><00><00><00>S)zTotal discrete output bits.c3<01>$K<00>|] }|jV<00><00> dSr/rIr;s rr3z3DeviceConfig.total_output_points.<locals>.<genexpr>Rs$<00><00><00><00>C<>C<><01>1<EFBFBD>8<EFBFBD>C<>C<>C<>C<>C<>Cr)rKrFr?s r<00>total_output_pointsz DeviceConfig.total_output_pointsPs+<00><00><12>C<>C<>T<EFBFBD>%@<40>%@<40>%B<>%B<>C<>C<>C<>C<>C<>Crc<01>$<00>d<01>|jD<00><00>S)Nc<01>$<00>g|] }|jdv<00> |<01><02>S))<02> analog_input<75>temperature_inputr:r;s rr<z5DeviceConfig.analog_input_modules.<locals>.<listcomp>Ws2<00><00>H<01>H<01>H<01>a<EFBFBD><14>:<3A>!F<>F<>F<><12>F<>F<>Frr>r?s r<00>analog_input_modulesz!DeviceConfig.analog_input_modulesVs*<00><00>H<01>H<01>4<EFBFBD><<3C>H<01>H<01>H<01> Hrc<01>$<00>d<01>|jD<00><00>S)Nc<01>(<00>g|]}|jdk<00> |<01><02>S)<01> analog_outputr:r;s rr<z6DeviceConfig.analog_output_modules.<locals>.<listcomp>[r=rr>r?s r<00>analog_output_modulesz"DeviceConfig.analog_output_modulesZrArc<01>X<00>td<01>|<00><00><00>D<00><00><00><00>S)z2Total 16-bit input registers (for FC04 bulk read).c3<01>$K<00>|] }|jV<00><00> dSr/rIr;s rr3z;DeviceConfig.total_analog_input_channels.<locals>.<genexpr>`s$<00><00><00><00>A<>A<><01>1<EFBFBD>8<EFBFBD>A<>A<>A<>A<>A<>Ar)rKrUr?s r<00>total_analog_input_channelsz(DeviceConfig.total_analog_input_channels^s+<00><00><12>A<>A<>T<EFBFBD>%><3E>%><3E>%@<40>%@<40>A<>A<>A<>A<>A<>Arc<01>X<00>td<01>|<00><00><00>D<00><00><00><00>S)zTotal 16-bit output registers.c3<01>$K<00>|] }|jV<00><00> dSr/rIr;s rr3z<DeviceConfig.total_analog_output_channels.<locals>.<genexpr>drJr)rKrYr?s r<00>total_analog_output_channelsz)DeviceConfig.total_analog_output_channelsbrMrc<01>$<00>d<01>|jD<00><00>S)z=All modules that are inputs (digital + analog + temperature).c<01>2<00>g|]}|jjdk<00>|<01><02>S)<01>input<75>r<00> directionr;s rr<z.DeviceConfig.input_modules.<locals>.<listcomp>js1<00><00>7<>7<>7<>a<EFBFBD><14>=<3D>*<2A>g<EFBFBD>5<>5<><12>5<>5<>5rr>r?s r<00> input_moduleszDeviceConfig.input_moduleshs$<00><00>7<>7<>4<EFBFBD><<3C>7<>7<>7<> 7rc<01>$<00>d<01>|jD<00><00>S)z8All modules that are outputs (digital + relay + analog).c<01>2<00>g|]}|jjdk
2<>2<>2<>2<>E<01>E<01>E<01>E<01>C<01>C<01>C<01>C<01>D<01>D<01>D<01>D<01> H<01>H<01>H<01>H<01>2<>2<>2<>2<>B<01>B<01>B<01>B<01>C<01>C<01>C<01>C<01> 7<>7<>7<>7<>
8<>8<>8<>8<>8<>8rr!c<01><><00>eZdZUded<ded<ded<ded<ded<d ed
<d ed <d ed<dZded<dZded<dZded<dZded<dZded<dS)<1A> LogicalIOr<00>name<6D>devicerr<00>pointzLiteral['input', 'output']rdr rrrzLiteral['bool', 'int']<5D>
value_typeN<EFBFBD> bool | None<6E> default_state<74>
int | None<6E> default_valuerr<00>DeviceConfig | None<6E>
device_refr,<00>
module_ref) rrrrrrrtrrvrwrrrrlrlss<><00><00><00><00><00><00><00> <0A>I<EFBFBD>I<EFBFBD>I<EFBFBD><0F>K<EFBFBD>K<EFBFBD>K<EFBFBD> <0A>I<EFBFBD>I<EFBFBD>I<EFBFBD><0E>J<EFBFBD>J<EFBFBD>J<EFBFBD>)<29>)<29>)<29>)<29><16><16><16><16>-<2D>-<2D>-<2D>-<2D>&<26>&<26>&<26>&<26>!%<25>M<EFBFBD>%<25>%<25>%<25>%<25> $<24>M<EFBFBD>$<24>$<24>$<24>$<24><1B>N<EFBFBD><1B><1B><1B><1B>&*<2A>J<EFBFBD>*<2A>*<2A>*<2A>*<2A>&*<2A>J<EFBFBD>*<2A>*<2A>*<2A>*<2A>*<2A>*rrlc<01><><00>eZdZUded<ded<ded<dZded <dZd
ed <dZded <dZd
ed <dZd
ed<dZ d
ed<dS)<10> SequenceStepr<00>t_msz2Literal['set_output', 'check_input', 'wait_input']<5D>actionr<00>signalNrq<00>staters<00>value<75>expected<65>expected_value<75> tolerance<63>
timeout_ms)
rrrrr}r~rr<>r<>r<>rrrryry<00>s<><00><00><00><00><00><00><00> <0A>I<EFBFBD>I<EFBFBD>I<EFBFBD>><3E>><3E>><3E>><3E><0F>K<EFBFBD>K<EFBFBD>K<EFBFBD><1D>E<EFBFBD><1D><1D><1D><1D><1C>E<EFBFBD><1C><1C><1C><1C> <20>H<EFBFBD> <20> <20> <20> <20>!%<25>N<EFBFBD>%<25>%<25>%<25>%<25> <20>I<EFBFBD> <20> <20> <20> <20>!<21>J<EFBFBD>!<21>!<21>!<21>!<21>!<21>!rryc<01>F<00>eZdZUded<ded<ee<05><04><00>Zded<dS)<08>Sequencerrm<00> descriptionr'<00>list[SequenceStep]<5D>stepsN)rrrrrrjr<>rrrr<>r<><00>sE<00><00><00><00><00><00><00> <0A>I<EFBFBD>I<EFBFBD>I<EFBFBD><14><14><14><14> %<25><05>d<EFBFBD> ;<3B> ;<3B> ;<3B>E<EFBFBD>;<3B>;<3B>;<3B>;<3B>;<3B>;rr<>c<01>F<00>eZdZUded<ded<ded<dd <0B>Zdd<0E>Zdd<10>ZdS)<15>Config<69>list[DeviceConfig]<5D>devices<65>list[LogicalIO]<5D>
logical_io<EFBFBD>list[Sequence]<5D> sequences<65> device_idrr+ruc<01>F<00><01>t<00>fd<01>|jD<00><00>d<00><00>S)Nc3<01>2<00>K<00>|]}|j<00>k<00> |V<00><00>dSr/<00>r")r1<00>dr<64>s <20>rr3z Config.device.<locals>.<genexpr><3E>s/<00><><00><00><00>B<>B<>1<EFBFBD><01><04> <09>0A<30>0A<30>Q<EFBFBD>0A<30>0A<30>0A<30>0A<30>B<>Br)r4r<>)r5r<>s `rrnz Config.device<63>s*<00><><00><13>B<>B<>B<>B<><04> <0C>B<>B<>B<>D<EFBFBD>I<>I<>Irrm<00>LogicalIO | Nonec<01>F<00><01>t<00>fd<01>|jD<00><00>d<00><00>S)Nc3<01>2<00>K<00>|]}|j<00>k<00> |V<00><00>dSr/<00>rm<00>r1<00>srms <20>rr3z Config.signal.<locals>.<genexpr><3E>s)<00><><00><00><00>B<>B<>1<EFBFBD>1<EFBFBD>6<EFBFBD>T<EFBFBD>><3E>><3E>Q<EFBFBD>><3E>><3E>><3E>><3E>B<>Br)r4r<><00>r5rms `rr|z Config.signal<61>s*<00><><00><13>B<>B<>B<>B<><04><0F>B<>B<>B<>D<EFBFBD>I<>I<>Ir<00>Sequence | Nonec<01>F<00><01>t<00>fd<01>|jD<00><00>d<00><00>S)Nc3<01>2<00>K<00>|]}|j<00>k<00> |V<00><00>dSr/r<>r<>s <20>rr3z"Config.sequence.<locals>.<genexpr><3E>s)<00><><00><00><00>A<>A<>1<EFBFBD>!<21>&<26>D<EFBFBD>.<2E>.<2E>Q<EFBFBD>.<2E>.<2E>.<2E>.<2E>A<>Ar)r4r<>r<>s `r<00>sequencezConfig.sequence<63>s*<00><><00><13>A<>A<>A<>A<><04><0E>A<>A<>A<>4<EFBFBD>H<>H<>HrN)r<>rr+ru)rmrr+r<>)rmrr+r<>)rrrrrnr|r<>rrrr<>r<><00>s<><00><00><00><00><00><00><00><1F><1F><1F><1F><1F><1F><1F><1F><1D><1D><1D><1D>J<01>J<01>J<01>J<01>J<01>J<01>J<01>J<01>I<01>I<01>I<01>I<01>I<01>Irr<>c<01><00>eZdZdS)<02> ConfigErrorN)rrrrrrr<>r<><00>s<00><00><00><00><00><00><08>Drr<><00>val<61>object<63>contextrr+<00>boolc<01><><00>t|t<00><00>r|St|t<00><00>r0|<00><00><00>dvrdS|<00><00><00>dvrdSt |<01>d|<00><02><03><00><00>)N)<04>true<75>yes<65>on<6F>1T)<04>false<73>no<6E>off<66>0Fz: expected boolean, got )<05>
isinstancer<EFBFBD>r<00>lowerr<72>)r<>r<>s r<00> _parse_boolr<6C><00>sy<00><00><11>#<23>t<EFBFBD><1C><1C><13><12>
<EFBFBD><11>#<23>s<EFBFBD><1B><1B><19> <0E>9<EFBFBD>9<EFBFBD>;<3B>;<3B>4<> 4<> 4<><17>4<EFBFBD> <0E>9<EFBFBD>9<EFBFBD>;<3B>;<3B>5<> 5<> 5<><18>5<EFBFBD>
<15><17>A<>A<>#<23>A<>A<>
B<EFBFBD>
B<EFBFBD>Br<00>path<74>
str | Pathc<01>Z<00>t|<00><00>}|<00><00><00>std|<00><00><02><00><00>t|<00><00>5}t j|<01><00>}ddd<02><00>n #1swxYwYt |t<00><00>std<03><00><00>t|<02> d<04><00>pg<00><00>}d<05>|D<00><00>}t|<02> d<06><00>pg|<04><00>}d<07>|D<00><00>}t|<02> d<08><00>pg|<06><00>}t|||<07> <09><00>S)
zHLoad and validate a YAML config file. Raises ConfigError on any problem.zConfig file not found: Nz3Config file must be a YAML mapping at the top levelr<6C>c<01><00>i|]
}|j|<01><02> Srr<>)r1r<>s r<00>
<dictcomp>zload.<locals>.<dictcomp><3E>s<00><00>+<2B>+<2B>+<2B>a<EFBFBD>!<21>$<24><01>+<2B>+<2B>+rr<>c<01><00>i|]
}|j|<01><02> Srr<>)r1r<>s rr<>zload.<locals>.<dictcomp><3E>s<00><00>0<>0<>0<><01>!<21>&<26>!<21>0<>0<>0rr<>)r<>r<>r<>) r<00>existsr<73><00>open<65>yaml<6D> safe_loadr<64><00>dict<63>_parse_devices<65>get<65>_parse_logical_io<69>_parse_sequencesr<73>)r<><00>f<>rawr<77><00>
device_mapr<EFBFBD><00>
signal_mapr<EFBFBD>s r<00>loadr<64><00>s^<00><00> <0F><04>:<3A>:<3A>D<EFBFBD> <0F>;<3B>;<3B>=<3D>=<3D><<3C><19>:<3A>D<EFBFBD>:<3A>:<3A>;<3B>;<3B>;<3B> <0A>d<EFBFBD><1A><1A> <20>q<EFBFBD><12>n<EFBFBD>Q<EFBFBD><1F><1F><03> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20> <20><><EFBFBD><EFBFBD> <20> <20> <20> <20> <16>c<EFBFBD>4<EFBFBD> <20> <20>Q<01><19>O<>P<>P<>P<><1F><03><07><07> <09> 2<> 2<> 8<>b<EFBFBD>9<>9<>G<EFBFBD>+<2B>+<2B>7<EFBFBD>+<2B>+<2B>+<2B>J<EFBFBD>"<22>3<EFBFBD>7<EFBFBD>7<EFBFBD><<3C>#8<>#8<>#><3E>B<EFBFBD>
<EFBFBD>K<>K<>J<EFBFBD>0<>0<>Z<EFBFBD>0<>0<>0<>J<EFBFBD>!<21>#<23>'<27>'<27>+<2B>"6<>"6<>"<<3C>"<22>j<EFBFBD>I<>I<>I<EFBFBD> <11>'<27>j<EFBFBD>I<EFBFBD> N<> N<> N<>Ns<00>A&<03>&A*<07>-A*<07>raw_listrjr<>c<01><><00>t|t<00><00>std<01><00><00>g}t<00><00>}t |<00><00>D<00>]<5D>\}}d|<03>d<03>}t|t
<00><00>st|<05>d<04><02><00><00>t |d|<05><00>}||vrt|<05>d|<06><02><03><00><00>|<02>|<06><00>t |d|<05><00>}t|<04> dd <09><00><00><00>}t|<04> d
d <0B><00><00><00>} t|<04> d d <0A><00><00><00>}
t|<04> d<0E><00>pg|<05><00>} d} d} t| d<10><00><11><00>D]0}|j dkr| |_ | |jz } <0C>| |_ | |jz } <0A>1|<01>t!|||| |
t| d<13><00><11><00><00><14><00><00><00><00><01><>|S)Nz'devices' must be a listzdevices[<5B>]<5D>: must be a mappingr"z: duplicate device id r#r$i<>r%rr&<00>2r*rc<01><00>|jSr/r0<00>r2s r<00><lambda>z _parse_devices.<locals>.<lambda><3E>s<00><00>q<EFBFBD>v<EFBFBD>r<00><01>key<65>coilc<01><00>|jSr/r0r<>s rr<>z _parse_devices.<locals>.<lambda> s<00><00>!<21>&<26>r)r"r#r$r%r&r*)r<>rjr<><00>set<65> enumerater<65><00> _require_str<74>addrr<><00>_parse_modules<65>sortedrrr<00>appendr!)r<>r<><00>seen_ids<64>ir<69><00>ctx<74>dev_idr#r$r%<00> poll_intervalr*<00> coil_offset<65>register_offsetr2s rr<>r<><00>s
<00><00> <15>h<EFBFBD><04> %<25> %<25>6<><19>4<>5<>5<>5<>"$<24>G<EFBFBD><1C><15><15>H<EFBFBD><1B>H<EFBFBD>%<25>%<25>) <0B>) <0B><06><01>3<EFBFBD><1D><11>o<EFBFBD>o<EFBFBD>o<EFBFBD><03><19>#<23>t<EFBFBD>$<24>$<24> ;<3B><1D><13>9<>9<>9<>:<3A>:<3A> :<3A><1D>c<EFBFBD>4<EFBFBD><13>-<2D>-<2D><06> <11>X<EFBFBD> <1D> <1D><1D><13>F<>F<>F<EFBFBD>F<>F<>G<>G<> G<><10> <0C> <0C>V<EFBFBD><1C><1C><1C>$<24>S<EFBFBD>&<26>#<23>6<>6<><04><1B>C<EFBFBD>G<EFBFBD>G<EFBFBD>F<EFBFBD>C<EFBFBD>0<>0<>1<>1<><04><1B>C<EFBFBD>G<EFBFBD>G<EFBFBD>I<EFBFBD>q<EFBFBD>1<>1<>2<>2<><07><1B>C<EFBFBD>G<EFBFBD>G<EFBFBD>$6<><02>;<3B>;<3B><<3C><<3C> <0A> <20><13><17><17><19>!3<>!3<>!9<>r<EFBFBD>3<EFBFBD>?<3F>?<3F><07><1C> <0B><1B><0F><17><07>%5<>%5<>6<>6<>6<> ,<2C> ,<2C>A<EFBFBD><10>~<7E><16>'<27>'<27>#.<2E><01> <20><1B>1<EFBFBD>8<EFBFBD>+<2B> <0B> <0B>#2<><01> <20><1F>1<EFBFBD>8<EFBFBD>+<2B><0F><0F><0F><0E><0E>|<7C><15><15><15><1B>*<2A><1A>7<EFBFBD>(8<>(8<>9<>9<>9<> 
<EFBFBD>
<EFBFBD>
<EFBFBD> <0B> <0B> <0B> <0B> <13>Nr<00>
parent_ctxr)c <01><00>t|t<00><00>st|<01>d<01><02><00><00>g}t<00><00>}t |<00><00>D<00>]=\}}|<01>d|<04>d<03>}t|t
<00><00>st|<06>d<04><02><00><00>t t|d|<06><00><00><00>}t|d|<06><00>}|dkrt|<06>d|<07><00><03><00><00>||vrt|<06>d |<07><00><03><00><00>|<03> |<07><00> t|<08><00>} n'#t$r}
t|<06>d
|
<EFBFBD><00><03><00>d<00>d}
~
wwxYwt |<05> d | j <00><00><00><00>} |<02>t||| | | j| j<00> <0C><00><00><00><00><01>?|S) Nz.modules: must be a listz .modules[r<>r<>rrrz: slot must be >= 1, got z: duplicate slot <20>: r)rrrrrr)r<>rjr<>r<>r<>r<>r<00>_requirer<65>r<>r <00>KeyErrorr<72>rr<>rrr) r<>r<>r*<00>
seen_slotsr<EFBFBD>r<>r<>r<00>mod_type<70>mt<6D>excrs rr<>r<>s<><00><00> <15>h<EFBFBD><04> %<25> %<25>C<01><19>Z<EFBFBD>A<>A<>A<>B<>B<>B<>"$<24>G<EFBFBD><1E>5<EFBFBD>5<EFBFBD>J<EFBFBD><1B>H<EFBFBD>%<25>%<25> <0B> <0B><06><01>3<EFBFBD><1B>*<2A>*<2A>a<EFBFBD>*<2A>*<2A>*<2A><03><19>#<23>t<EFBFBD>$<24>$<24> ;<3B><1D><13>9<>9<>9<>:<3A>:<3A> :<3A><16>x<EFBFBD><03>V<EFBFBD>S<EFBFBD>1<>1<>2<>2<><04><1F><03>V<EFBFBD>S<EFBFBD>1<>1<><08> <0F>!<21>8<EFBFBD>8<EFBFBD><1D><13>E<>E<>t<EFBFBD>E<>E<>F<>F<> F<> <0F>:<3A> <1D> <1D><1D><13>=<3D>=<3D>t<EFBFBD>=<3D>=<3D>><3E>><3E> ><3E><12><0E><0E>t<EFBFBD><1C><1C><1C> 9<> <20><18>*<2A>*<2A>B<EFBFBD>B<EFBFBD><42><17> 9<> 9<> 9<><1D><13>o<EFBFBD>o<EFBFBD><03>o<EFBFBD>o<EFBFBD>.<2E>.<2E>D<EFBFBD> 8<><38><EFBFBD><EFBFBD><EFBFBD> 9<><39><EFBFBD><EFBFBD><15>S<EFBFBD>W<EFBFBD>W<EFBFBD>X<EFBFBD>r<EFBFBD>y<EFBFBD>1<>1<>2<>2<><06><0F><0E><0E>|<7C><15><19><1A><19><17>[<5B><1B><1F> 
<EFBFBD>
<EFBFBD>
<EFBFBD> <0B> <0B> <0B> <0B> <13>Ns<00>3D<02>
D'<05> D"<05>"D'r<><00>dict[str, DeviceConfig]r<>c<01><><00>t|t<00><00>std<01><00><00>g}t<00><00>}t |<00><00>D<00>]<5D>\}}d|<04>d<03>}t|t
<00><00>st|<06>d<04><02><00><00>t |d|<06><00>}t |d|<06><00>}tt|d|<06><00><00><00>} tt|d|<06><00><00><00>}
t |d |<06><00>} ||vrt|<06>d
|<07><02><03><00><00>|<03> |<07><00>| d vrt|<06>d | <0B><02><03><00><00>|<01>
|<08><00>} | <0C>t|<06>d |<08><02><03><00><00>| <0C> | <09><00>} | <0A>+d<0E>| j D<00><00>}t|<06>d|<08>d| <09>d|<0E><00><07><00><00>| j j| kr)t|<06>d| <0B>d| j<00>d| j j<00><02><07><00><00>|
dks |
| jkr t|<06>d|
<EFBFBD>d| <09>d| j<00>d<19><08><00><00>d}d|vr=| j jr| dkrt|<06>d<1C><02><00><00>t%|d|dz<00><00>}d}d|vr9| j jr| dkrt|<06>d<1F><02><00><00>t|d<00><00>}| j|
dz
z}|<02>t-||| |
| | j| j| j j|||| | <0A> <20> <00> <00><00><00><02><>|S)!Nz'logical_io' must be a listz logical_io[r<>r<>rmrnrrordz: duplicate signal name )rbrhz-: direction must be 'input' or 'output', got z: references unknown device c<01><00>g|] }|j<00><02>
Srr0r;s rr<z%_parse_logical_io.<locals>.<listcomp>^s<00><00>1<>1<>1<><01>Q<EFBFBD>V<EFBFBD>1<>1<>1rz : device z has no module at slot z. Available slots: z: signal direction z does not match module type z
which is rz: point z! out of range for module at slot z (module has z points, 1-based)rrrhz8: default_state is only valid for digital output signalsz.default_statertz7: default_value is only valid for analog output signals) rmrnrrordrrrprrrtrrvrw)r<>rjr<>r<>r<>r<>r<>rr<>r<>r<>r6r*rrdrr<00>
is_digitalr<EFBFBD><00> is_analogrr<>rlrrrp)r<>r<><00>signals<6C>
seen_namesr<EFBFBD>r<>r<>rmr<>rrord<00>dev<65>mod<6F>slotsrrrtrs rr<>r<>;s<><00><00> <16>h<EFBFBD><04> %<25> %<25>9<><19>7<>8<>8<>8<>!<21>G<EFBFBD><1E>5<EFBFBD>5<EFBFBD>J<EFBFBD><1B>H<EFBFBD>%<25>%<25>O <0B>O <0B><06><01>3<EFBFBD> <20>A<EFBFBD> <20> <20> <20><03><19>#<23>t<EFBFBD>$<24>$<24> ;<3B><1D><13>9<>9<>9<>:<3A>:<3A> :<3A> <20><13>f<EFBFBD>c<EFBFBD>2<>2<><04> <20><13>h<EFBFBD><03>4<>4<><06><17><08><13>f<EFBFBD>c<EFBFBD>2<>2<>3<>3<><04><17><08><13>g<EFBFBD>s<EFBFBD>3<>3<>4<>4<><05> <20><13>k<EFBFBD>3<EFBFBD>7<>7<> <09> <0F>:<3A> <1D> <1D><1D><13>F<>F<>d<EFBFBD>F<>F<>G<>G<> G<><12><0E><0E>t<EFBFBD><1C><1C><1C> <14>/<2F> /<2F> /<2F><1D><16>R<>R<>Y<EFBFBD>R<>R<><0E><0E> <0E><19>n<EFBFBD>n<EFBFBD>V<EFBFBD>$<24>$<24><03> <0E>;<3B><1D><13>L<>L<>&<26>L<>L<>M<>M<> M<><11>!<21>!<21>$<24>'<27>'<27><03> <0E>;<3B>1<>1<>S<EFBFBD>[<5B>1<>1<>1<>E<EFBFBD><1D><16>,<2C>,<2C><16>,<2C>,<2C>$<24>,<2C>,<2C>$)<29>,<2C>,<2C><0E><0E> <0E>
<0F>?<3F> $<24> <09> 1<> 1<><1D><16>S<01>S<01>9<EFBFBD>S<01>S<01>"<22>x<EFBFBD>S<01>S<01>58<35>_<EFBFBD>5N<35>S<01>S<01><0E><0E> <0E>
<11>1<EFBFBD>9<EFBFBD>9<EFBFBD><05><03>
<EFBFBD>*<2A>*<2A><1D><16>=<3D>=<3D><05>=<3D>=<3D><04>=<3D>=<3D>"<22>z<EFBFBD>=<3D>=<3D>=<3D><0E><0E> <0E> &*<2A> <0A> <1A>c<EFBFBD> !<21> !<21><16>?<3F>-<2D> <12><19>h<EFBFBD>1F<31>1F<31>!<21><1A>T<>T<>T<><12><12><12>(<28><03>O<EFBFBD>(<<3C>c<EFBFBD>DT<44>>T<>U<>U<>M<EFBFBD>%)<29> <0A> <1A>c<EFBFBD> !<21> !<21><16>?<3F>,<2C> <12> <09>X<EFBFBD>0E<30>0E<30>!<21><1A>S<>S<>S<><12><12><12> <20><03>O<EFBFBD> 4<>5<>5<>M<EFBFBD><1D>+<2B>u<EFBFBD>q<EFBFBD>y<EFBFBD>9<><0E><0F><0E><0E>y<EFBFBD><15><19><15><17><1F><18>\<5C><1C>)<29><1A><EFBFBD>1<>'<27>'<27>)<29><1A><1A>
<EFBFBD>
<EFBFBD>
<EFBFBD> <0B> <0B> <0B> <0B> <13>Nrr<><00>dict[str, LogicalIO]r<>c<01>0<00>t|t<00><00>std<01><00><00>g}t<00><00>}t |<00><00>D]<5D>\}}d|<04>d<03>}t|t
<00><00>st|<06>d<04><02><00><00>t |d|<06><00>}|<05>dd<07><00>}||vrt|<06>d|<07><02><03><00><00>|<03>|<07><00>t|<05>d <09><00>pg||<06><00>} |<02>
t||| <09>
<EFBFBD><00><00><00><00><>|S) Nz'sequences' must be a listz
sequences[r<>r<>rmr<><00>z: duplicate sequence name r<>)rmr<>r<>) r<>rjr<>r<>r<>r<>r<>r<>r<><00> _parse_stepsr<73>r<>)
r<EFBFBD>r<>r<>r<>r<>r<>r<>rmr<>r<>s
rr<>r<><00>s4<00><00> <16>h<EFBFBD><04> %<25> %<25>8<><19>6<>7<>7<>7<> "<22>I<EFBFBD><1E>5<EFBFBD>5<EFBFBD>J<EFBFBD><1B>H<EFBFBD>%<25>%<25> T<01> T<01><06><01>3<EFBFBD><1F>1<EFBFBD><1F><1F><1F><03><19>#<23>t<EFBFBD>$<24>$<24> ;<3B><1D><13>9<>9<>9<>:<3A>:<3A> :<3A>"<22>3<EFBFBD><06><03>4<>4<><04><19>g<EFBFBD>g<EFBFBD>m<EFBFBD>R<EFBFBD>0<>0<> <0B> <0F>:<3A> <1D> <1D><1D><13>H<>H<><04>H<>H<>I<>I<> I<><12><0E><0E>t<EFBFBD><1C><1C><1C><1C>S<EFBFBD>W<EFBFBD>W<EFBFBD>W<EFBFBD>-<2D>-<2D>3<><12>Z<EFBFBD><13>E<>E<><05><11><18><18><18>t<EFBFBD><1B>E<EFBFBD>R<>R<>R<>S<>S<>S<>S<> <14>rr<>c<01><><00>t|t<00><00>st|<02>d<01><02><00><00>g}t|<00><00>D<00>]<5D>\}}|<02>d|<04>d<03>}t|t<00><00>st|<06>d<04><02><00><00>t t |d|<06><00><00><00>}t|d|<06><00>}t|d|<06><00>} |dkrt|<06>d |<07><00><03><00><00>|d
vrt|<06>d |<08><02><03><00><00>|<01>| <09><00>}
|
<EFBFBD>t|<06>d | <09><02><03><00><00>t||| <09> <0A><00>} |dkr<>|
j
dkrt|<06>d| <09>d<11><04><00><00>|
j dkr6d|vrt|<06>d<14><02><00><00>t|d|dz<00><00>| _ <00>n+d|vrt|<06>d<17><02><00><00>t |d<00><00>| _n<>|dvr<>|
j dkr8d|vrt|<06>d|<08>d<1B><04><00><00>t|d|dz<00><00>| _nYd|vrt|<06>d|<08>d<1E><04><00><00>t |d<00><00>| _d|vrt |d<00><00>| _nd| _|d krTd!|vrt|<06>d"<22><02><00><00>t |d!<00><00>| _| jdkrt|<06>d#| j<00><00><03><00><00>|<03>| <0B><00><00><02><>|<03>d$<24><00>%<25><00>|S)&Nz.steps: must be a listz.steps[r<>r<>rzr{r|rz: t_ms must be >= 0, got )<03>
set_output<EFBFBD> check_input<75>
wait_inputzC: action must be 'set_output', 'check_input', or 'wait_input', got z: references unknown signal )rzr{r|r<>rhz#: set_output action used on signal u. which is an input — use check_input insteadr<64>r}z5: set_output step for digital signal requires 'state'z.stater~z4: set_output step for analog signal requires 'value')r<>r<>rr<>z, step for digital signal requires 'expected'z .expectedr<64>z1 step for analog signal requires 'expected_value'r<>r<>r<>z-: wait_input step requires 'timeout_ms' fieldz: timeout_ms must be > 0, got c<01><00>|jSr/)rz)r<>s rr<>z_parse_steps.<locals>.<lambda>s<00><00>Q<EFBFBD>V<EFBFBD>rr<>)r<>rjr<>r<>r<>rr<>r<>r<>ryrdrpr<>r}r~rr<>r<>r<>r<><00>sort) r<>r<>r<>r<>r<>r<>r<>rzr{r|<00>sig<69>steps rr<>r<><00>s<><00><00> <16>h<EFBFBD><04> %<25> %<25>A<01><19>Z<EFBFBD>?<3F>?<3F>?<3F>@<40>@<40>@<40> "<22>E<EFBFBD><1B>H<EFBFBD>%<25>%<25>I<1B>I<1B><06><01>3<EFBFBD><1B>(<28>(<28>A<EFBFBD>(<28>(<28>(<28><03><19>#<23>t<EFBFBD>$<24>$<24> ;<3B><1D><13>9<>9<>9<>:<3A>:<3A> :<3A><14>X<EFBFBD>c<EFBFBD>6<EFBFBD>3<EFBFBD>/<2F>/<2F>0<>0<><04><1D>c<EFBFBD>8<EFBFBD>S<EFBFBD>1<>1<><06><1D>c<EFBFBD>8<EFBFBD>S<EFBFBD>1<>1<><06> <0F>!<21>8<EFBFBD>8<EFBFBD><1D><13>E<>E<>t<EFBFBD>E<>E<>F<>F<> F<> <11>D<> D<> D<><1D><16>#<23>#<23><1E>#<23>#<23><0E><0E> <0E>
<19>n<EFBFBD>n<EFBFBD>V<EFBFBD>$<24>$<24><03> <0E>;<3B><1D><13>L<>L<>&<26>L<>L<>M<>M<> M<><1B><14>f<EFBFBD>V<EFBFBD>D<>D<>D<><04> <11>\<5C> !<21> !<21><12>}<7D><08>(<28>(<28>!<21><1A>E<01>E<01>v<EFBFBD>E<01>E<01>E<01><12><12><12><13>~<7E><16>'<27>'<27><1A>#<23>%<25>%<25>%<25><1E>U<>U<>U<><16><16><16>)<29><13>W<EFBFBD><1C>s<EFBFBD>X<EFBFBD>~<7E>F<>F<><04>
<EFBFBD>
<EFBFBD><1A>#<23>%<25>%<25>%<25><1E>T<>T<>T<><16><16><16>!<21><13>W<EFBFBD><1C>.<2E>.<2E><04>
<EFBFBD>
<EFBFBD> <13>4<> 4<> 4<><12>~<7E><16>'<27>'<27><1D>S<EFBFBD>(<28>(<28>%<25><1E>V<>V<>&<26>V<>V<>V<><16><16><16>!,<2C>C<EFBFBD>
<EFBFBD>O<EFBFBD>S<EFBFBD>;<3B>=N<> O<> O<><04> <0A> <0A>#<23>3<EFBFBD>.<2E>.<2E>%<25><1E>,<2C>,<2C>&<26>,<2C>,<2C>,<2C><16><16><16>'*<2A>#<23>.><3E>*?<3F>&@<40>&@<40><04>#<23><1E>#<23>%<25>%<25>%(<28><13>[<5B>)9<>%:<3A>%:<3A>D<EFBFBD>N<EFBFBD>N<EFBFBD>%&<26>D<EFBFBD>N<EFBFBD><15><1C>%<25>%<25><1F>s<EFBFBD>*<2A>*<2A>%<25><1E>M<>M<>M<><16><16><16>#&<26>c<EFBFBD>,<2C>&7<>"8<>"8<><04><0F><17>?<3F>a<EFBFBD>'<27>'<27>%<25><1E>O<>O<>d<EFBFBD>o<EFBFBD>O<>O<><16><16><16> <0E> <0C> <0C>T<EFBFBD><1A><1A><1A><1A>
<EFBFBD>J<EFBFBD>J<EFBFBD>#<23>#<23>J<EFBFBD>$<24>$<24>$<24> <10>Lrr<>r<>r<>r<>c<01>D<00>||vrt|<02>d|<01>d<02><04><00><00>||S)Nz: missing required field '<27>')r<>)r<>r<>r<>s rr<>r<>s3<00><00>
<EFBFBD>!<21>|<7C>|<7C><19>S<EFBFBD>B<>B<>C<EFBFBD>B<>B<>B<>C<>C<>C<> <0C>S<EFBFBD>6<EFBFBD>Mrc <01><><00>t|||<02><00>}t|t<00><00>s)t|<02>d|<01>dt |<03><00>j<00><00><05><00><00>|S)N<>.z: expected string, got )r<>r<>rr<>rr)r<>r<>r<>r<>s rr<>r<>sX<00><00>
<12>1<EFBFBD>c<EFBFBD>3<EFBFBD>
<1F>
<1F>C<EFBFBD> <15>c<EFBFBD>3<EFBFBD> <1F> <1F>U<01><19>S<EFBFBD>S<>S<>3<EFBFBD>S<>S<>t<EFBFBD>C<EFBFBD>y<EFBFBD>y<EFBFBD>?Q<>S<>S<>T<>T<>T<> <0E>Jr)r<>r<>r<>rr+r<>)r<>r<>r+r<>)r<>rjr+r<>)r<>rjr<>rr+r))r<>rjr<>r<>r+r<>)r<>rjr<>r<>r+r<>)r<>rjr<>r<>r<>rr+r<>)r<>r<>r<>rr<>rr+r<>)r<>r<>r<>rr<>rr+r)!<21>__doc__<5F>
__future__rr<><00> dataclassesrr<00>pathlibr<00>typingr<00> module_typesr r
r r rr!rlryr<>r<><00> Exceptionr<6E>r<>r<>r<>r<>r<>r<>r<>r<>r<>rrr<00><module>r
s<><00><01><04><04>4#<23>"<22>"<22>"<22>"<22>"<22> <0B> <0B> <0B> <0B>(<28>(<28>(<28>(<28>(<28>(<28>(<28>(<28><18><18><18><18><18><18><1A><1A><1A><1A><1A><1A>P<>P<>P<>P<>P<>P<>P<>P<>P<>P<>P<>P<> <0B> <1C> <1C> <1C> <1C> <1C> <1C> <1C> <0B><19> <1C> <0B>98<>98<>98<>98<>98<>98<>98<> <0B><19>98<>x <0B>+<2B>+<2B>+<2B>+<2B>+<2B>+<2B>+<2B> <0B><19>+<2B>& <0B>"<22>"<22>"<22>"<22>"<22>"<22>"<22> <0B><19>"<22>" <0B><<3C><<3C><<3C><<3C><<3C><<3C><<3C> <0B><19><<3C>  <0B> I<01> I<01> I<01> I<01> I<01> I<01> I<01> <0B><19> I<01>& <09> <09> <09> <09> <09>)<29> <09> <09> <09>C<01>C<01>C<01>C<01>O<01>O<01>O<01>O<01>62<13>2<13>2<13>2<13>j%<13>%<13>%<13>%<13>PZ<13>Z<13>Z<13>Z<13>z<15><15><15><15>6U<11>U<11>U<11>U<11>x<12><12><12><12> <0F><0F><0F><0F><0F>r